5X35023

An introduction to the VersaClock 3S development kit, and a step-by-step guide on how to program the device using a PC.

The development kit consists of two boards: the main board is used for evaluating the device (taking measurements, etc.), and also features a USB port for connecting it to the PC. The daughter card that sits on top has a socket and is used for programming additional devices.

Programming the device is fairly straight forward. You connect the board to the PC via USB. You then open up IDT's Timing Commander software and load the appropriate personality file (the one the corresponds to the device you are programming). Once you connect to the board, you can simply type in the desired output frequency, and it will change on the fly. More advanced settings can also be made using the GUI.

Presented by Eddy Van-Keulen, applications engineer at IDT. For more information about IDT's VersaClock products, visit www.IDT.com/go/versaclock.

Related Resources

• 5X35023 - VersaClock 3S Programmable Clock Generator with Integrated Crystal
• VersaClock Programmable Clocks

This video introduces IDT's VersaClock 3S Programmable Clock Generators, known for their innovative power-saving features and compact design that eliminates multiple timing components. Designed for applications in consumer, industrial, computing, and automotive sectors, these devices offer low power consumption and low jitter scalability, meeting PCI Express® Gen 1/2/3 standards. 

Key features highlighted include Proactive Power Saving, Performance-Power Balancing, Dynamic Frequency Control, and Overshoot Reduction Technology. The video showcases the VersaClock 3S models, including the 5P35023 with multiple outputs and the 5P35021 with a 32.768KHz clock for RTC reference, supported by IDT's Timing Commander software for easy programming.

Related Resources

• VersaClock Programmable Clocks
• Programmable Clock Generators, Low-Power, Programmable Oscillators

Transcript

Hi. I'm Nick at the EEWeb Tech Lab and today I have the latest generation of programmable clocks from IDT.
 
VersaClock^® 3S is a family of IDT programmable clocks with innovative features designed specifically for applications requiring low power such as consumer applications and high-performance PCI Express^®. VersaClock 3S series has built-in unique features such as Proactive Power Saving, Performance Power Balancing, Overshoot Reduction Technology, and Dynamic Frequency Control.
 
Proactive Power Saving, or PPS, makes the VersaClock 3S the world's first smart generator with downstream device power mode monitor. By monitoring the status of the downstream device's clock the VersaClock 3S is able to dynamically switch its clock when a downstream device enters sleep mode from a MHz output to a 32 kHz output. This dynamic frequency switching decreases a current of each output clock from 5 or 10 milliamps, depending on the application, down to a tiny 2 microamps.
 
Performance Power Balancing, or PPB, allows a user to achieve targeted performance while optimizing power consumption. This targeted power mode can be selected using IDT's GUI called the Timing Commander. The Timing Commander GUI is a free download and can be found at idt.com.
 
IDT's patented Overshoot Reduction Technology affords a smooth frequency transition and keeps a frequency at the targeted frequency. This ORT feature eliminates the overshoot and undershoot common with tradition PLL designs during frequency transitions, which can cause a system to fail.
 
The user-programmable Dynamic Frequency Control, or DFC, provides a user with up to four preprogrammed frequencies for audio clocks, video clocks, overclocking, or motor speed control. These frequencies can be changed on the fly by using either the hardware pins or the I²C registers.
 
Other device features include multiple function OE pins, the support for two differential clocks and three single-ended clocks, and a built-in watchdog timer.
 
So let's take a look at some of the IDT products.
 
So this is the evaluation board and it's designed for customers who want higher-performance measurements. The IC in the middle, this is the VersaClock 3S. And the USB connector, it accepts 2.0 or 3.0 USB. The mode selector switch is right here. And jumper configurations are here to configure the onboard voltage regulators. A crystal clock is right here for reference on the reference signal. And then the user guide, or the manual, can be downloaded from idt.com.
 
This is the programming board and it's available for customers who don't need the high-performance of the evaluation board. It accepts both types of socket boards for either the 20 pin or the 24 pin IC. The USB connection, again, is 2.0 or 3.0. It has onboard DC regulatorsthat are actually on the back side. One is here and one is here. And it's compatible with the IDT Timing Commander GUI. And, again, the user guide is downloadable from idt.com.
 
And this is the socket board. I'll open it up here. There's just a blank part in here right now, but this is where your IC would go. So once you have it in there, then it just connects to this programming board with the sockets, like that. And then you're ready to program.
 
So this is a Timing Commander GUI. I'm going to start it up. I've downloaded it and I've also downloaded the personality file specific for the VersaClock 3S. I'm loading the file now and the personality file shows up. So these two here. And I'll select this one. Takes just a minute for it to load up.
 
So the tabs here - there are three. The diagram obviously shows a pinout of the IC. A tab for bit sets that lets you select the bits. And then a tab for registers. It lets you go in and select different register settings.
 
So if we go back to the diagram pin. This icon here lets you save your settings. This connects to the chip. And this is connection settings here. So the interface or you can change the I²C slave device.
 
And this is the optimization control for PLLs here. VDD, you can change the voltages. The signal types you can change here. And then the spread-spectrum clocking, you can change these, disable them, or enable them.
 
IDT's VersaClock 3S family is the industry's most versatile multi-PLL clock generation and crystal consolidation solution for applications including consumer, industrial, communications, medical, automotive, and battery-powered. These devices are offered in small 3x3 or 4x4 QFN packages which makes them ideal for cost-sensitive and dense applications when there's a desire to reduce BOM parts and/or the PCB footprint.
 
For more information visit idt.com.

The VersaClock 3S devices deliver innovative power-saving features while saving board space by eliminating the need for multiple discrete timing components. Delivering low power and low jitter scalability, the VersaClock 3S devices meet requirements for widely used standards including PCI Express^® Gen 1/2/3, and are ideal for consumer, industrial, computing, and automotive applications.

The 5P35023 and 5P35021 chips deliver a unique set of features offering an optimal combination of performance, power, and flexibility. 

Related Resources

• VersaClock Programmable Clocks

TRANSCRIPT

VersaClock 3S is a family of programmable clocks that deliver innovative features for an optimal blend of performance, power, and flexibility. The compact products can replace multiple crystals, or crystal oscillators, for a smaller board footprint while maintaining extremely low power consumption and are ideal for consumer, industrial, computing, and automotive applications.

VersaClock 3S offers less than three picoseconds of RMS phase jitter and supports PCI Express Generation 1, 2, and 3 requirements. A built-in, digitally controlled oscillator provides a low-frequency clock at less than two microamps per real-time clock operation with several years of operation using a coin-cell battery. Three PLLs optimized for different performance levels offer operation from 2mA to 15mA, and the device features several unique features to balance power and performance. Frequencies up to 160MHz on LVCMOS and up to 500MHz on differential outputs are supported and one-time programmable memory is available for programming.

The VersaClock 3S devices are offered in small 3mm x 3mm and 4mm x 4mm QFN packages. The larger device features three LVCMOS and two differential outputs along with a reference clock output. The smaller device offers a single LVCMOS and two differential clock outputs.

VersaClock 3S offers several unique features. A performance power balancing feature supported by the Renesas Timing Commander GUI easily optimizes power consumption based on target performance. A patented overshoot frequency control feature eliminates frequency overshoot or undershoot which is common with traditional PLL designs during frequency transitions. Dynamic frequency control offers smooth and glitch-free transitions between up to four pre-programmed frequencies for on-the-fly frequency changes.

And, VersaClock 3S is the world's first intelligent clock generator with a downstream device power-mode monitor. The proactive power-saving feature monitors the clock status using the Xout pin of the downstream device and will switch to a very low-power 32KHz clock during sleep mode and switch back to normal operation when the downstream device wakes up.

Other device features include a multi-function output that enables pins, along with a built-in watchdog timer. Evaluation and programmer boards along with our Timing Commander software are available to assist with development. The VersaClock 3S family offers an ideal combination of versatility, performance, and low power for a variety of applications. For more information, please visit www.renesas.com/versaclock. Thank you.

Description

IDT provides a brief overview of the timing solutions optimized for various configurations using the NXP (Freescale) QorIQ / Layerscape processors.

Presented by Ron Wade, PCI Express timing expert. For more information about IDT's timing solutions, visit www.IDT.com/go/clocks.

TRANSCRIPT

So, hi there, this is Ron Wade again and we're going to be talking about timing solutions that IDT has for NXP's QorIQ and Layerscape CPU. And in the middle here, what I've drawn, in the middle of the box here, is what I refer to as our all-in-one solutions. These are single chips that may have all the clocks you need to build your system around the NXP CPUs. So, the three parts I have listed here are the 6P49V205, the 5P49V5907, and 5P49V5908. These provide a mix of the clocks that were needed over here for the CPU cores and SerDes clocks, and they're all on a single chip. If these suit your needs, these are ideal, these are the smallest core footprint parts to use. 
 
The other approach besides all-in-one is the building block approach, and I'm going to start over here on the left side with the CPU clocks and the memory controller. For this solution over here, we have the 5P49V5901, or it could be a 6901, depending on your requirements. And, this guy has the most flexibility as far as programming up any combination of DDR clock or CPU clock that you want, as well as the 24 MHz USB clock and a 125 MHz clock. 
 
If you're using the Layerscape CPU with the reduced oscillator mode where you have the 100 MHz non-spread clock coming in, you might want to consider the 9FGV0 series or the 9FGL0 series. These are very high-performance PCI Express clock generators, the V being a 1.8 volt part and the L being a 3.3 volt part that are available. The terminations are integrated, they're very low power and they also have some extra copies in case SerDes is a PCI Express SerDes. So, this is the ideal solution if you want to go building block over here. 
 
And then for the SerDes clocks, we've got the 125 MHz differential for Gigabit Ethernet, the 156 MHz for 10 gig, and the 100 MHz for PCIe. We have again a different set of flavors we can go with. We have the 5P49V6901, which is a better performing, lower phase jitter version of the 5901 over here. This guy's ideal if you have a mix of these SerDes frequencies in your design. If you're in a homogeneous environment, for instance, where everything's PCI Express or everything is 125 MHz, then you could use the 9FGV parts, or I'll use an output from over there, over on this side for the 100 MHz output, or you could use these guys programmed up to be 125 as well. Or if you've got a 125 coming from over there, you can use one of the 9DVD buffers which are the 1.8V buffers to fan that out. Likewise, we have similar parts with 3.3-volt power supplies, if that's what you prefer. The 9FGL0 series, it should give you the 100 to the 125, and the 9DVL0 series which can provide a fanout buffer for any of these three frequencies.
 
So, that's an overview of the timing solutions for NXP's QorIQ and Layerscape CPUs. This is Ron Wade at IDT again. Thanks for watching and see you next time.

IDT provides a brief tutorial on the timing solutions required for NXP (Freescale) QorIQ / Layerscape processor-based systems.

Presented by Ron Wade, PCI Express timing expert. For more information about IDT's timing solutions, visit www.IDT.com/go/clocks.

TRANSCRIPT

Hi there, this is Ron Wade with IDT and today we're going to talk about NXP, formerly known as Freescale, CPUs. Specifically the QorIQ and Layerscape CPUs and the timing requirements that they have. So, it's basically divided into a couple of parts here. There's some timing that the CPU itself requires and then there's timing that depends upon your system and the number of SerDes links you have in your design and in your CPU. So, if we talk about the CPU part itself, we have the CPU cores which get a clock, and we have the memory controller inside the CPUs which gets a clock as well. And the memory controller clock is called the DDR clock. The CPU clock is called the SYS_CCB clock in the Freescale nomenclature, excuse me, the NXP nomenclature and those frequencies - they're single-ended clocks and they range, like the DDR from 66.66 MHz up to 100 MHz, and the CPU clocks range from 66.66 up to 133.33 MHz, in some cases. Those are single-ended LVCMOS input clocks. Additionally, some of the CPUs have a USB interface which may require a 24 MHz single-ended clock. And there's also an Ethernet interface built in, a one-gigabit Ethernet interface, that is, takes a 125 MHz single-ended clock as well and that's at 2.5 volts.
 
So, in the Layerscape series of CPUs which are based on the ARM core, Freescale has put into them, what they call a reduced oscillator mode where all the clocks over here basically are reduced by a single differential 100 MHz non-spreading clock, and this saves you from having to figure out and generate all these clocks. However, it has to be non-spread because the USB clock is also derived from it, so, if you're planning to use spread spectrum, you really can't use this mode. And, currently, it's only available in the Layerscape devices, not the legacy QorIQ devices.
 
So, that's the basics for the CPU and the memory controller. Then the SerDes is really dependent upon the particular CPU you're using and how many SerDes lanes you need in your design. So, the SerDes clocks, on the other hand, basically range from 125 MHz differential clock for Gigabit Ethernet, if you're using 10 Gigabit Ethernet, a 156.25 MHz clock is required. And then if you're using PCI Express, you'd use a standard 100 MHz PCI Express clock. All these happen to be differential and the number of SerDes lanes and their capabilities depends on the CPU you're using. So, this gives you an outline of how to just do a quick tally of what kind of clocks you need and in another video, I'll talk about the solutions that IDT has for NXP's devices.