Features
- Logic and mixed-signal circuits
- Highly versatile macrocells
- Read back protection (read lock)
- 1.8V (±5%) to 5V (±10%) VDD
- 1.8V (±5%) to 5V (±10%) VDD2 (VDD2 ≤ VDD)
- Operating temperature range: -40°C to 85°C
- RoHS-compliant/Halogen-free
- AEC-Q100 Grade 1
- Macrocells Overview
- Four analog comparators (ACMP)
- Two voltage references (Vref)
- Nineteen combination function macrocells
- Three selectable DFF/latch or 2-bit LUTs
- One selectable continuous DFF/latch or 3-bit LUT
- Four selectable DFF/latch or 3-bit LUTs
- One selectable pipe delay or 3-bit LUT
- One selectable programmable function generator or 2-bit LUT
- Five 8-bit delays/counters or 3-bit LUTs
- Two 16-bit delays/counters or 4-bit LUTs
- Two deglitch filters with edge detectors
- State machine
- Eight states
- Flexible input logic from state transitions
- Serial communications
- I2C protocol compliant
- Pipe delay – 16-stage/3-output (part of combination function macrocell)
- Programmable delay
- One inverter
- Two oscillators (OSC)
- Configurable 25kHz/2MHz
- 25MHz RC oscillator
- Crystal oscillator
- Power-On Reset (POR)
- Eight Byte RAM + OTP user memory
- RAM memory space that is readable and writable via I2C
- User-defined initial values transferred from OTP
Description
The SLG46538-A programmable mixed-signal matrix with asynchronous state machine and dual supply provides a small, low-power component for commonly used mixed-signal functions. Users can create their circuit designs by programming the one-time programmable (OTP) non-volatile memory (NVM) to configure the interconnect logic, the I/O pins, and macrocells of the SLG46538-A. This highly versatile device allows for a wide variety of mixed-signal functions to be designed within a very small, low-power single integrated circuit.
The additional power supply (VDD2) on the SLG46538-A allows interfacing between two independent voltage domains within the same design. Pins dedicated to each power supply can be configured as inputs, outputs, or both, dynamically controlled by internal logic, to operate across both VDD and VDD2 voltage domains. Using the available macrocells, designers can implement mixed-signal functions bridging both domains or simply pass through level translation in both high-to-low and low-to-high directions.
Parameters
| Attributes | Value |
|---|---|
| GPIOs (#) | 17 |
| LUTs (Max) (#) | 17 |
| D Flip-flops (DFFs) (#) | 8 |
| ACMP Channels (#) | 4 |
| CNT/DLY (Max) (#) | 7 |
| # of Programable Delays (#) | 1 |
| Pipe Delay | 16-stage |
| Interface | I2C |
| Nominal VDD | 1.71 - 5.5 |
| Oscillator Type | Conf. OSC, RC OSC |
| Temperature Sensor (ch) (#) | 1 |
| Automotive Rating | AEC-Q100 (Grade 1) |
| Special Features | ASM (8 states) |
| Temp. Range (°C) | -40 to +125°C |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) |
|---|---|---|
| TQFN | 4.0 x 4.0 | 20 |
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