Description
The AT25SF321B is a member of our standard class code and data storage solutions designed for 3V systems in which program code is shadowed from Flash memory into embedded or external RAM for execution.
The architecture includes erase block sizes that are optimized to meet the needs of today's code and data storage applications and three security register pages for unique device serialization, system-level Electronic Serial Number (ESN) storage, locked key storage, etc.
- Universally compatible pinout and command set
- Standard block architecture
- Supports Dual I/O, Quad I/O and XiP operation
- Continuous read, wrap and burst modes for XiP
Parameters
| Attributes | Value |
|---|---|
| Memory Class | Standard Flash |
| Memory Density | 32 |
| Operating Voltage Range (V) | 2.7 - 3.6 |
| Speed | 108 MHz |
| Interface | Single, Dual, Quad SPI |
| Temp. Range (°C) | -40 to +85°C |
| Deep Power Down (µA) | 1 |
| Read Current (mA) | 3.3 |
| Key Benefit | Standard features |
Application Block Diagrams
| Level 2 EV Charger Modular EVSE system with advanced connectivity for efficient EV charging and management. | |
| Smart HMI System with Voice & Display Interfaces Smart HMI system with 32-bit MCU supports GUI, voice I/O, IoT connectivity, and fast development tools. | |
| Robot Vacuum Cleaner This smart robot vacuum features environment mapping, anti-drop, obstacle detection, auto-recharge, app control. | |
| 1-Phase Power Meter Flexible, MCU-controlled, high-end 1-phase power meter for greater control and scalability. |
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| Part Number | Status | Longevity | Stock | Package | Budgetary Price (USD) | Sample Catalog | Carrier Type | Moisture Sensitivity Level (MSL) | Country of Assembly |
|---|---|---|---|---|---|---|---|---|---|
| AT25SF321B-DWF | Active | 2030 Jan | Out of Stock | DWF | <a href="https://www.renesas.com/samplecomponents/scripts/samplecenter/adestotech?cmd=menu" title="Request Samples" rel="noreferrer">Request Samples</a> | 1 | |||
| AT25SF321B-MHB-T | Active | 2030 Jan | In Stock | DFN | 1ku | $0.49 | <a href="https://www.renesas.com/samplecomponents/scripts/samplecenter/adestotech?cmd=menu" title="Request Samples" rel="noreferrer">Request Samples</a> | Tape & Reel | 1 | TAIWAN |
| AT25SF321B-SHB-B | Active | 2030 Jan | In Stock | SOIC-W | 1ku | $0.38 | <a href="https://www.renesas.com/samplecomponents/scripts/samplecenter/adestotech?cmd=menu" title="Request Samples" rel="noreferrer">Request Samples</a> | Tube | 1 | TAIWAN |
| AT25SF321B-SHB-T | Active | 2030 Jan | In Stock | SOIC-W | 1ku | $0.39 | <a href="https://www.renesas.com/samplecomponents/scripts/samplecenter/adestotech?cmd=menu" title="Request Samples" rel="noreferrer">Request Samples</a> | Tape & Reel | 1 | TAIWAN |
| AT25SF321B-SSHB-B | Active | 2030 Jan | In Stock | SOIC-N | 1ku | $0.38 | <a href="https://www.renesas.com/samplecomponents/scripts/samplecenter/adestotech?cmd=menu" title="Request Samples" rel="noreferrer">Request Samples</a> | Tube | 1 | PHILIPPINES |
| AT25SF321B-SSHB-T | Active | 2030 Jan | In Stock | SOIC-N | 1ku | $0.38 | <a href="https://www.renesas.com/samplecomponents/scripts/samplecenter/adestotech?cmd=menu" title="Request Samples" rel="noreferrer">Request Samples</a> | Tape & Reel | 1 | PHILIPPINES |
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- Application NotePDF 884 KB R10AN0038EU0100 Rev.1.00 Mar 10, 2026This application note discusses endurance and data retention in NOR Flash memory products. It describes the structure and operation of the NOR Flash transistor, the mechanisms of NOR Flash device failure and oxide degradation which limit endurance and data retention. It explains JEDEC-based test procedures for certifying endurance and data retention specifications and ways to mitigate limitations. The first part of this document and the appendix provide background for understanding the issue. The later sections describe practical scenarios of interest to most customers.
- DatasheetAT25SF321B DatasheetRECOMMENDEDPDF 1.85 MB DS-AT25SF321B-179 Dec 02, 2025Describes the features, functions, command set, performance parameters, package pinout, package details, and the ordering number of the AT25SF321B. All the information in this document is to aid engineers to use the 32Mbit 2.7V to 3.6V, SPI serial NOR flash in their design.
- Application NotePDF 695 KB AN503 Sep 05, 2025Explores thermal resistance in integrated circuits (ICs) and details its role in managing heat from power consumption to ensure reliable operation. Proper thermal management enhances IC performance and longevity. Thermal resistance, measured in °C/W, quantifies heat flow resistance from the silicon die to the environment or PCB, with key types including junction-to-case (θJC), case-to-ambient (θCA), junction-to-ambient (θJA), and junction-to-board (θJB).
- Application NotePDF 2.62 MB AN500 Feb 13, 2024AI-generated Summary: NOR Flash memory requires an erase operation before programming, which occurs in three phases: Pre-Program, Erase, and Recovery. The erase process affects entire blocks simultaneously, not byte-by-byte. Memory cells use floating gate MOSFETs to store data, organized into arrays of rows (Word-Lines) and columns (Bit-Lines). Physical Blocks contain multiple Logical Blocks and share common p-wells and Bit-Lines, impacting operation. Smaller Logical Blocks enable improved erase performance through parallelization. Understanding these processes and potential interruptions is crucial for designing reliable systems.
- Application NotePDF 710 KB AN502 Jan 24, 2024AI-generated Summary: Renesas NOR flash devices require decoupling capacitors close to VCC and GND pins to stabilize voltage, typically 1 μF with an optional 100 nF capacitor. Pull-up resistors are recommended on CS#, WP#/IO2, and HOLD#/IO3 pins to ensure proper signal states and facilitate debugging. Signal routing should minimize trace length and maintain a solid ground plane for high-speed signals. Power supply must rise monotonically during power-up. Basic system bring-up involves verifying installation, voltage levels, and SPI communication using manufacturer/device ID commands. Software drivers depend on host MCU architecture; Renesas offers example drivers and support. Correct erase/program sequences include write-enable, erase/program commands, and status checks. Tools for programming include flash loader plug-ins and debug probes. Switching from single to quad-SPI involves setting the quad-enable bit, changing pin functions. Dummy cycles introduce necessary wait times during read commands to accommodate latency.
- GuidePDF 790 KB SPI_NOR_Flash_Product_Guide_PBFLASH03102022rev-C Jun 16, 2023
- Product Change NoticePDF 195 KB Mar 06, 2023
- Application Note
- DocumentPDF 1 MB R10DS0315EU0000 Rev.0.00 Jun 28, 2022
- Application NotePDF 794 KB May 12, 2022AI-generated Summary: Renesas NOR flash devices implement multiple protection methods to safeguard memory arrays, status registers, flash states, and resets from accidental or intentional modifications. Protection types include hardware-based write protection via the WP pin and software-based protection through commands controlling status registers and memory blocks. Memory array protection schemes include individual block protection, allowing sector-level lock/unlock, and memory edge protection, which protects contiguous regions aligned to memory edges. Status register protection indirectly secures memory by blocking changes to protection states. Detailed command sets and register bits configure these protections, ensuring robust flash memory integrity.
- Model - Verilog
- Model - IBIS
- Application NotePDF 663 KB Oct 18, 2021AI-generated Summary: Proper power-up and power-down sequencing is critical for NOR Flash memory operation to ensure reliable system performance. The power supply voltage must ramp up monotonically without dips, reaching the minimum operational voltage within specified timing to avoid corrupted initialization. Reset methods, including hardware and JEDEC resets, help ensure the device starts from a known state. Brown-out conditions and power cycling require careful handling to prevent data corruption and ensure stable operation. The document covers power sequencing, reset types, brown-out recovery, power-down, and power-saving modes, providing essential guidelines for system engineers and application developers.
- DatasheetAT25SF321B DatasheetRECOMMENDEDPDF 1.85 MB DS-AT25SF321B-179 Dec 02, 2025Describes the features, functions, command set, performance parameters, package pinout, package details, and the ordering number of the AT25SF321B. All the information in this document is to aid engineers to use the 32Mbit 2.7V to 3.6V, SPI serial NOR flash in their design.
Recommended Documents (1)
- DatasheetAT25SF321B DatasheetRECOMMENDEDPDF 1.85 MB DS-AT25SF321B-179 Dec 02, 2025Describes the features, functions, command set, performance parameters, package pinout, package details, and the ordering number of the AT25SF321B. All the information in this document is to aid engineers to use the 32Mbit 2.7V to 3.6V, SPI serial NOR flash in their design.
Datasheets (1)
- GuidePDF 790 KB SPI_NOR_Flash_Product_Guide_PBFLASH03102022rev-C Jun 16, 2023
Manuals & Guides (1)
- Application NotePDF 884 KB R10AN0038EU0100 Rev.1.00 Mar 10, 2026This application note discusses endurance and data retention in NOR Flash memory products. It describes the structure and operation of the NOR Flash transistor, the mechanisms of NOR Flash device failure and oxide degradation which limit endurance and data retention. It explains JEDEC-based test procedures for certifying endurance and data retention specifications and ways to mitigate limitations. The first part of this document and the appendix provide background for understanding the issue. The later sections describe practical scenarios of interest to most customers.
- Application NotePDF 695 KB AN503 Sep 05, 2025Explores thermal resistance in integrated circuits (ICs) and details its role in managing heat from power consumption to ensure reliable operation. Proper thermal management enhances IC performance and longevity. Thermal resistance, measured in °C/W, quantifies heat flow resistance from the silicon die to the environment or PCB, with key types including junction-to-case (θJC), case-to-ambient (θCA), junction-to-ambient (θJA), and junction-to-board (θJB).
- Application NotePDF 2.62 MB AN500 Feb 13, 2024AI-generated Summary: NOR Flash memory requires an erase operation before programming, which occurs in three phases: Pre-Program, Erase, and Recovery. The erase process affects entire blocks simultaneously, not byte-by-byte. Memory cells use floating gate MOSFETs to store data, organized into arrays of rows (Word-Lines) and columns (Bit-Lines). Physical Blocks contain multiple Logical Blocks and share common p-wells and Bit-Lines, impacting operation. Smaller Logical Blocks enable improved erase performance through parallelization. Understanding these processes and potential interruptions is crucial for designing reliable systems.
- Application NotePDF 710 KB AN502 Jan 24, 2024AI-generated Summary: Renesas NOR flash devices require decoupling capacitors close to VCC and GND pins to stabilize voltage, typically 1 μF with an optional 100 nF capacitor. Pull-up resistors are recommended on CS#, WP#/IO2, and HOLD#/IO3 pins to ensure proper signal states and facilitate debugging. Signal routing should minimize trace length and maintain a solid ground plane for high-speed signals. Power supply must rise monotonically during power-up. Basic system bring-up involves verifying installation, voltage levels, and SPI communication using manufacturer/device ID commands. Software drivers depend on host MCU architecture; Renesas offers example drivers and support. Correct erase/program sequences include write-enable, erase/program commands, and status checks. Tools for programming include flash loader plug-ins and debug probes. Switching from single to quad-SPI involves setting the quad-enable bit, changing pin functions. Dummy cycles introduce necessary wait times during read commands to accommodate latency.
Application Notes & White Papers (9)
- Product Change NoticePDF 195 KB Mar 06, 2023
- Product Change NoticePDF 528 KB Jun 26, 2020
Product Notices (PCN, EOL, etc) (3)
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Marketing Collateral (1)
- DocumentPDF 1 MB R10DS0315EU0000 Rev.0.00 Jun 28, 2022
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- Model - IBIS
- Model - Verilog
- Development ToolµISP is a compact standalone and universal solution, specifically designed for production environments, based on Algocrafts WriteNow! Technology. This is a standard tool for many families and devices and supports multi programming protocol (JTAG, SPI, UART, DAP, SWD, I2C, BDM, custom protocol, etc).Provided By: Algocraft Srl
- Development ToolWriteNow! Series of In-System Programmers is a breakthrough in the programming industry. The programmers support a large number of devices (microcontrollers, memories, CPLDs and other programmable devices) from various manufacturers and have a compact size for easy ATE/fixture integration. They work in standalone or connected to a ...Provided By: Algocraft Srl
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- Model - IBIS
- Model - Verilog
Simulation Models (2)
- Development ToolµISP is a compact standalone and universal solution, specifically designed for production environments, based on Algocrafts WriteNow! Technology. This is a standard tool for many families and devices and supports multi programming protocol (JTAG, SPI, UART, DAP, SWD, I2C, BDM, custom protocol, etc).Provided By: Algocraft Srl
- Development ToolWriteNow! Series of In-System Programmers is a breakthrough in the programming industry. The programmers support a large number of devices (microcontrollers, memories, CPLDs and other programmable devices) from various manufacturers and have a compact size for easy ATE/fixture integration. They work in standalone or connected to a ...Provided By: Algocraft Srl
Partner Solutions (2)
Level 2 EV Charger Reference Design
This modular electric vehicle supply equipment (EVSE) system simplifies development and accelerates deployment of smart electric vehicle (EV) chargers. Our controller board stacks over a power board and supports flexible 1-phase to 3-phase charging up to 22kW. We integrate Wi-Fi, Bluetooth® Low... Read More
Support Communities
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AT25SF321B and AT25SF321 Programming
Is there a difference between AT25SF321B and AT25SF321 other than speed and operating voltage and with a programmer that can program AT25SF321, can I program AT25SF321B too?
Sep 22, 2022 -
Detecting #WP pin state on AT25FF321A and AT25SF321B
For both the AT25FF321A and AT25SF321B that are configured for hardware protection with the #WP pin (SRP1,0 = 01) what is the lowest impact way of detecting the state of the #WP pin (ability to write to status registers)? As most of the R/W status register ...
Nov 14, 2021 -
AT25SF321B volatile status register bits
Which bits in the status register of the AT25SF321B are volatile, and which are non-volatile? The datasheet talks about volatile and non-volatile bits, but I can't find a table of which ones are which. In particular, is the Quad Enable bit volatile or non volatile (i.e ...
Sep 11, 2023
Knowledge Base
-
"B" suffix NOR flash Part numbers
... a newer part than a part without the suffix "B". It has enhanced features. Example AT25SF321 vs AT25SF321B ==> AT25SF321B is a newer part than AT25SF321. AT25SF321B has new additional commands and improved performance. AT25SF321B has a 108 MHz Maximum Operating Frequency vs 104 MHz for AT25SF321 AT25SF321B Operating voltages 2 ...
Apr 13, 2023