RC310

Features

1.8V/2.5V/3.3V flexible power rails
Typical 150fs RMS 12kHz to 20MHz phase jitter
5/8/12 outputs with integrated crystal options
1kHz to 650MHz LVDS/LP-HCSL outputs
1kHz to 200MHz LVCMOS outputs
Programmable hardware configuration select-pins
PCIe Gen 5/6/7 ready
Space saving packages 4mm × 4mm, 5mm × 5mm, 6mm × 6mm
JESD204B/C support on differential or single-ended outputs with DC-coupling or AC-coupling
Digital holdover and hitless switching
Integrated crystal option for space saving and BOM optimization
ITU-T G.8262 and G.82621 compliant for easy synchronized Ethernet application

Find Other Products in Jitter Attenuators

VersaClock7 Programmable Clock Generator Overview

RC310xx Block Diagram

Description

The RC31xxxB (RC31008B and RC31012B) are small form factor, fully integrated, low-power, high-performance jitter attenuators with network synchronization capabilities. The family supports JEDEC JESD204B/C for converter synchronization and SyncE for network-based synchronization. The RC31xxxB are ideal for driving converter circuits in wireless and wireline infrastructure, data center equipment, and instrumentation applications. The devices are members of Renesas' high-performance VersaClock^®7 family

Up to 27 configurations reusable across multiple designs may be stored in on-chip One-Time Programmable (OTP) memory or external I²C EEPROM. Redundant input is available for backup and used as a reference clock where needed.

This device is factory-configurable.
Try the Custom Part Configuration Utility.

Parameters

Attributes	Value
Inputs (#)	2
Input Type	LVDS, LP-HCSL, LVCMOS
Product Category	VersaClock, IEEE 1588, Jitter Attenuators, Network Synchronization, PCI Express Clocks, Programmable Clocks
Diff. Outputs	5, 8, 12
Output Type	LVDS, LP-HCSL, LVCMOS
Output Voltage (V)	1.8V, 2.5V, 3.3V
Input Freq (MHz)	1 - 650
Phase Jitter Typ RMS (ps)	0.15
Output Freq Range (MHz)	0.001 - 650
Fractional Output Dividers (#)	3
Core Voltage (V)	1.8V, 2.5V, 3.3V
Output Banks (#)	6
Advanced Features	JESD204B/C, Spread Spectrum, Hitless Switching

Package Options

Pkg. Type	Pkg. Dimensions (mm)	Lead Count (#)	Pitch (mm)
LGA	4.0 x 4.0 x 1.0	32	0.4
LGA	5.0 x 5.0 x 1.7	40	0.4
LGA	6.0 x 6.0 x 0.9	48	0.4
VFQFPN	5.0 x 5.0 x 0.9	40	0.4
VFQFPN	6.0 x 6.0 x 0.9	48	0.4

Applications

Switches/Routers
Synchronous Ethernet (SyncE) equipment
Telecom Time Slave Clock (T-TSC) equipment
Jitter attenuation for 10/25/40/100/200/400 Gbps Ethernet PHYs or switches
Small cell for 4.5G and 5G

This device is factory-configurable.
Try the Custom Part Configuration Utility.

Part Number	Status	Samples	Longevity	Stock	Package	Lead Count (#)	Carrier Type	Moisture Sensitivity Level (MSL)	Pkg. Dimensions (mm)	Qty. per Reel (#)	Diff. Outputs	Input Type	Outputs (#)	Package Area (mm²)	Qty. per Carrier (#)	Pb (Lead) Free	Pb Free Category	Temp. Range (°C)
RC31005BQ00GL2#BB0	Active	Available	2040 Apr	Out of Stock	LGA	32#	Tray	3	4.0 x 4.0 x 1.0	0	5	LVDS, LP-HCSL, LVCMOS			490#	Yes	e3 Sn	-40 to 85°C
RC31005BQ00GL2#KB0	Active	N/A	2040 Apr	Out of Stock	LGA	32#	Reel	3	4.0 x 4.0 x 1.0	4000#	5	LVDS, LP-HCSL, LVCMOS			0	Yes	e3 Sn	-40 to 85°C
RC31005BQ01GL2#BB0	Active	Available	2040 Apr	Out of Stock	LGA	32#	Tray	3	4.0 x 4.0 x 1.0	0	5	LVDS, LP-HCSL, LVCMOS			490#	Yes	e3 Sn	-40 to 85°C
RC31005BQ01GL2#KB0	Active	N/A	2040 Apr	Out of Stock	LGA	32#	Reel	3	4.0 x 4.0 x 1.0	4000#	5	LVDS, LP-HCSL, LVCMOS			0	Yes	e3 Sn	-40 to 85°C
RC31008B000GND#BB0	Active	Available	2040 Apr	Out of Stock	VFQFPN	40#	Tray	3	5.0 x 5.0 x 0.9	0	8	LVDS, LP-HCSL, LVCMOS	16#	25mm²	490#	Yes	e3 Sn	-40 to 85°C
RC31008B000GND#KB0	Active	N/A	2040 Apr	Out of Stock	VFQFPN	40#	Reel	3	5.0 x 5.0 x 0.9	2500#	8	LVDS, LP-HCSL, LVCMOS	16#	25mm²	0	Yes	e3 Sn	-40 to 85°C
RC31008B001GND#BB0	Active	Available	2040 Apr	In Stock	VFQFPN	40#	Tray	3	5.0 x 5.0 x 0.9	0	8	LVDS, LP-HCSL, LVCMOS	16#	25mm²	490#	Yes	e3 Sn	-40 to 85°C
RC31008B001GND#KB0	Active	N/A	2040 Apr	Out of Stock	VFQFPN	40#	Reel	3	5.0 x 5.0 x 0.9	2500#	8	LVDS, LP-HCSL, LVCMOS	16#	25mm²	0	Yes	e3 Sn	-40 to 85°C
RC31008BQ00GL2#BD0	Active	Available	2040 Apr	Out of Stock	LGA	40#	Tray	3	5.0 x 5.0 x 1.7	0	8	LVDS, LP-HCSL, LVCMOS	16#	25mm²	490#	Yes	e4 Au	-40 to 85°C
RC31008BQ00GL2#KD0	Active	N/A	2040 Apr	Out of Stock	LGA	40#	Reel	3	5.0 x 5.0 x 1.7	3000#	8	LVDS, LP-HCSL, LVCMOS	16#	25mm²	0	Yes	e4 Au	-40 to 85°C
RC31008BQ01GL2#BD0	Active	Available	2040 Apr	Out of Stock	LGA	40#	Tray	3	5.0 x 5.0 x 1.7	0	8	LVDS, LP-HCSL, LVCMOS	16#		490#	Yes	e4 Au	-40 to 85°C
RC31008BQ01GL2#KD0	Active	N/A	2040 Apr	Out of Stock	LGA	40#	Reel	3	5.0 x 5.0 x 1.7	3000#	8	LVDS, LP-HCSL, LVCMOS	16#		0	Yes	e4 Au	-40 to 85°C
RC31012B000GNA#BB0	Active	Available	2040 Apr	In Stock	VFQFPN	48#	Tray	3	6.0 x 6.0 x 0.9	0	12	LVDS, LP-HCSL, LVCMOS	24#	36mm²	490#	Yes	e3 Sn	-40 to 85°C
RC31012B000GNA#KB0	Active	N/A	2040 Apr	Out of Stock	VFQFPN	48#	Reel	3	6.0 x 6.0 x 0.9	2500#	12	LVDS, LP-HCSL, LVCMOS	24#	36mm²	0	Yes	e3 Sn	-40 to 85°C
RC31012B001GNA#BB0	Active	Available	2040 Apr	Out of Stock	VFQFPN	48#	Tray	3	6.0 x 6.0 x 0.9	0	12	LVDS, LP-HCSL, LVCMOS	24#	36mm²	490#	Yes	e3 Sn	-40 to 85°C
RC31012B001GNA#KB0	Active	N/A	2040 Apr	Out of Stock	VFQFPN	48#	Reel	3	6.0 x 6.0 x 0.9	2500#	12	LVDS, LP-HCSL, LVCMOS	24#	36mm²	0	Yes	e3 Sn	-40 to 85°C
RC31012BQ00GL3#BB0	Active	Available	2040 Apr	Out of Stock	LGA	48#	Tray	3	6.0 x 6.0 x 0.9	0	12	LVDS, LP-HCSL, LVCMOS	24#		490#	Yes	e3 Sn	-40 to 85°C
RC31012BQ00GL3#KB0	Active	N/A	2040 Apr	Out of Stock	LGA	48#	Reel	3	6.0 x 6.0 x 0.9	4000#	12	LVDS, LP-HCSL, LVCMOS	24#		0	Yes	e3 Sn	-40 to 85°C
RC31012BQ01GL3#BB0	Active	Available	2040 Apr	Out of Stock	LGA	48#	Tray	3	6.0 x 6.0 x 0.9	0	12	LVDS, LP-HCSL, LVCMOS	24#		490#	Yes	e3 Sn	-40 to 85°C
RC31012BQ01GL3#KB0	Active	N/A	2040 Apr	Out of Stock	LGA	48#	Reel	3	6.0 x 6.0 x 0.9	4000#	12	LVDS, LP-HCSL, LVCMOS	24#		0	Yes	e3 Sn	-40 to 85°C
RC31005AQ00GL2#BB0	Obsolete	N/A		Out of Stock	LGA	32#	Tray	3	4.0 x 4.0 x 1.0	0	5	LVDS, LP-HCSL, LVCMOS	10#	16mm²	490#	Yes	e3 Sn	-40 to 85°C
RC31008A000GND#BB0	Obsolete	N/A		Out of Stock	VFQFPN	40#	Tray	3	5.0 x 5.0 x 0.9	0	8	Crystal, LVDS, LP-HCSL, LVCMOS	16#	25mm²	490#	Yes	e3 Sn	-40 to 85°C
RC31008A000GND#KB0	Obsolete	N/A		Out of Stock	VFQFPN	40#	Reel	3	5.0 x 5.0 x 0.9	2500#	8	Crystal, LVDS, LP-HCSL, LVCMOS	16#	25mm²	0	Yes	e3 Sn	-40 to 85°C
RC31008A001GND#BB0	Obsolete	N/A		In Stock	VFQFPN	40#	Tray	3	5.0 x 5.0 x 0.9	0	8	Crystal, LVDS, LP-HCSL, LVCMOS	16#	25mm²	490#	Yes	e3 Sn	-40 to 85°C
RC31008A001GND#KB0	Obsolete	N/A		Out of Stock	VFQFPN	40#	Reel	3	5.0 x 5.0 x 0.9	2500#	8	Crystal, LVDS, LP-HCSL, LVCMOS	16#	25mm²	0	Yes	e3 Sn	-40 to 85°C
RC31008AQ00GL2#BD0	Obsolete	N/A		In Stock	LGA	40#	Tray	3	5.0 x 5.0 x 1.7	0	8	LVDS, LP-HCSL, LVCMOS	16#	25mm²	490#	Yes	e4 Au	-40 to 85°C
RC31008AQ00GL2#KD0	Obsolete	N/A		Out of Stock	LGA	40#	Reel	3	5.0 x 5.0 x 1.7	3000#	8	LVDS, LP-HCSL, LVCMOS	16#	25mm²	0	Yes	e4 Au	-40 to 85°C
RC31012A000GNA#BB0	Obsolete	N/A		Out of Stock	VFQFPN	48#	Tray	3	6.0 x 6.0 x 0.9	0	12	Crystal, LVDS, LP-HCSL, LVCMOS	24#	36mm²	490#	Yes	e3 Sn	-40 to 85°C
RC31012A000GNA#KB0	Obsolete	N/A		Out of Stock	VFQFPN	48#	Reel	3	6.0 x 6.0 x 0.9	2500#	12	Crystal, LVDS, LP-HCSL, LVCMOS	24#	36mm²	0	Yes	e3 Sn	-40 to 85°C
RC31012A001GNA#BB0	Obsolete	N/A		Out of Stock	VFQFPN	48#	Tray	3	6.0 x 6.0 x 0.9	0	12	Crystal, LVDS, LP-HCSL, LVCMOS	24#	36mm²	490#	Yes	e3 Sn	-40 to 85°C
RC31012A001GNA#KB0	Obsolete	N/A		Out of Stock	VFQFPN	48#	Reel	3	6.0 x 6.0 x 0.9	2500#	12	Crystal, LVDS, LP-HCSL, LVCMOS	24#	36mm²	0	Yes	e3 Sn	-40 to 85°C

Filters

Application Note
VersaClock 7 Reference Schematics and Power Filtering Recommendations
PDF 992 KB R31AN0045EU0103 Rev.1.03 Nov 01, 2025
AI-generated Summary: VersaClock 7 devices support various crystal interface modes including crystal oscillator, LVCMOS overdrive, and differential signal input. The devices feature flexible general-purpose inputs (GPI) configurable as input clocks or control signals, and GPIO pins supporting multiple states for configuration. Serial communication supports I2C with pull-up resistors and SPI with configurable GPIO pins. Output drivers support multiple signaling standards such as LVDS, LP-HCSL, LVPECL, CML, and SSTL with appropriate coupling and termination. Power supply design divides core and output driver voltages, recommending separate power filtering per domain to minimize noise, with options for combined filtering to save PCB space. Detailed reference schematics and power filtering topologies guide optimal design and noise reduction.
Overview
VersaClock Family Overview
PDF 379 KB R31DS0004EU0003 Rev.0.03 Oct 23, 2025
Application Note
PLL Loop Filter Design and Fine Tuning
PDF 1.53 MB R31AN0034EU0102 Rev.1.02 Oct 21, 2025
AI-generated Summary: PLL loop filter design involves selecting component values to ensure stable operation and optimized phase noise. The loop bandwidth depends on parameters like charge pump current, VCO gain, and feedback divider. Second and third order passive loop filters are common, with specific calculations for cutoff, zero, and pole frequencies guiding component selection. Proper tuning of loop bandwidth enhances PLL stability and phase noise performance, demonstrated through lab experiments and calculation examples.
Application Note
Choosing a Crystal for VersaClock 7 Devices
PDF 404 KB R31AN0029EU0103 Rev.1.03 Oct 13, 2025
AI-generated Summary: Crystal selection for VersaClock 7 devices requires meeting specific frequency, ESR, load capacitance, and drive level specifications to ensure stable oscillator operation. Recommended crystals range from 8 to 80 MHz, with ESR limits varying by frequency band. A detailed list of acceptable crystals from various manufacturers, including their frequency tolerance, stability, aging, and temperature range, guides optimal crystal choice based on application needs. For example, a 50 MHz crystal suits 100 MHz output clock synthesizers. Frequency tolerance and aging parameters can be customized per application requirements.
Application Note
Choosing the Right Crystal for Clocking Devices
PDF 326 KB R31AN0027EU0101 Rev.1.01 Sep 24, 2025
AI-generated Summary: Selecting the appropriate crystal for clocking devices requires considering parameters such as nominal frequency, frequency tolerance, load capacitance, equivalent series resistance (ESR), operating temperature, drive level, and aging tolerance. Clock synthesizers benefit from crystals with integer-related frequencies to minimize jitter, while jitter attenuators should avoid integer or near-integer frequency ratios to prevent spurs. Higher crystal frequencies improve phase noise performance. Load capacitance affects oscillation frequency and startup reliability, and ESR must meet device specifications to ensure proper operation. Frequency variation combines tolerance, stability, and aging, which must align with application needs. Drive level ratings prevent premature aging and damage.
Model - IBIS
RC310 and RC210 IBIS Model
ZIP 998 KB Sep 10, 2025
Datasheet
RC310xxB Datasheet
RECOMMENDED
PDF 881 KB R31DS0010EU0124 Rev.1.24 Feb 03, 2025
The RC310xxB are high-performance programmable jitter attenuators with network synchronization capabilities. The devices support JEDEC JESD204B/C for converter synchronization, and SyncE for network-based synchronization. The RC310xxB are ideal for driving converter circuits in wire-line infrastructure, data center equipment, and instrumentation applications. This document describes the main design and operational characteristics for RC310xxB devices, including pin information, specifications, applications information, and packaging.
Product Change Notice
PCN# : 240019 Add alternate assembly locations on select VFQFPN packages and transfer assembly location on select PLCC package
PDF 1003 KB Nov 20, 2024
Application Note
VersaClock 7 (VC7) Internal Capacitance Configuration
PDF 406 KB R31AN0076EU0100 Rev.1.00 May 31, 2024
AI-generated Summary: Internal capacitance within the VersaClock® 7 (VC7) device is configured using Renesas IC Toolbox software (RICBox). Load capacitance on the crystal is calculated by considering internal stray capacitance (fixed at 8.2pF), external stray capacitance from PCB traces, and adjustable trimming capacitance. The trimming capacitance can be set in 0.42pF steps from 0 to 26.46pF. Bench setup for trimming involves using evaluation boards (RC21008/RC21012 EVBs), frequency counters, and RICBox software to measure and adjust the crystal frequency by tuning load capacitance. The document details step-by-step procedures for hardware setup, software configuration, and frequency measurement to optimize crystal trimming for accurate oscillator performance.
Product Change Notice
PCN# : 240002 (R1) VersaClock 7 Family revision update
PDF 225 KB May 20, 2024
Application Note
VersaClock 7 (VC7) Fanout Buffer Mode for PCI Express
PDF 1.67 MB R31AN0070EU0100 Rev.1.00 Mar 22, 2024
AI-generated Summary: VC7 initially outputs a 100MHz clock using an onboard crystal reference, then switches to a CLKIN reference upon toggling a GPIO (PERST#). Fanout buffer mode applies to Bank4, Bank5, and Bank6, with specific output pins supporting fanout modes depending on the device variant. Setup involves configuring the evaluation board, signal generator, frequency counter, and RICBox software. Crystal trimming is recommended to reduce phase noise spurs. CLKIN0 or CLKIN1 can be used as fanout sources, with detailed steps to configure clock inputs, fanout buffer mode, outputs, and GPIOs for signal loss and reset indication. The document also covers transient measurements and enabling additional banks.
Product Change Notice
PCN# : 240002 VersaClock 7 Family revision update
PDF 224 KB Mar 18, 2024
Report
RC310xx ITUT-T G.8262, ITU-T G.8262.1 Compliance Report
PDF 3.77 MB R31UZ0006EU0100 Rev.1.00 Dec 18, 2023
Application Note
VersaClock 7 Input to Output Adjustable Delay/Advance
PDF 1.28 MB R31AN0064EU0100 Rev.1.00 Nov 15, 2023
AI-generated Summary: VersaClock 7 devices enable precise control of clock edge delay or advance from input to output, adjustable in fine increments based on the VCO frequency. The delay range spans approximately ±12.8 ns with 25 ps granularity at a 10 GHz VCO frequency. Setup involves using RC31008A or RC31012A evaluation kits, an oscilloscope configured for delay measurement, and the RICBox software with specific settings files. Optional clock edge alignment can be performed via register adjustments to synchronize input and output edges. Delay or advance values are programmed through the RICBox GUI, allowing customizable timing shifts for clock signals.
Application Note
VersaClock 7 EEPROM Conversion: Enabling the VC7 Evaluation Board for EEPROM Loading
PDF 588 KB Sep 21, 2023
AI-generated Summary: Enable EEPROM loading on the VersaClock 7 evaluation board by using Renesas IC Toolbox (RICBox). Connect to the VC7 board via RICBox, access the OTP/EEPROM block diagram, and activate the conversion feature to allow EEPROM loading. Generate and save an EEPROM configuration file, scan the I2C bus for EEPROM detection, and program the EEPROM device using RICBox. Only the AT24C16 EEPROM chip is supported for this process.

Datasheets (1)

Datasheet
RC310xxB Datasheet
RECOMMENDED
PDF 881 KB R31DS0010EU0124 Rev.1.24 Feb 03, 2025
The RC310xxB are high-performance programmable jitter attenuators with network synchronization capabilities. The devices support JEDEC JESD204B/C for converter synchronization, and SyncE for network-based synchronization. The RC310xxB are ideal for driving converter circuits in wire-line infrastructure, data center equipment, and instrumentation applications. This document describes the main design and operational characteristics for RC310xxB devices, including pin information, specifications, applications information, and packaging.

Manuals & Guides (3)

Guide
RC310xx Programming Guide
RECOMMENDED
PDF 2.42 MB R31US0022EU0101 Rev.1.01 Aug 14, 2023
Manual - Software
RICBox GUI Software Manual for VersaClock 7
PDF 1.73 MB R31US0020EU0100 Rev.1.00 Aug 16, 2022
Manual - Hardware
VersaClock 7 PCB Layout Guidelines Manual
PDF 485 KB R31UH0017EU0100 Rev.1.00 Aug 04, 2022

Application Notes & White Papers (16)

Application Note
VersaClock 7 Reference Schematics and Power Filtering Recommendations
PDF 992 KB R31AN0045EU0103 Rev.1.03 Nov 01, 2025
AI-generated Summary: VersaClock 7 devices support various crystal interface modes including crystal oscillator, LVCMOS overdrive, and differential signal input. The devices feature flexible general-purpose inputs (GPI) configurable as input clocks or control signals, and GPIO pins supporting multiple states for configuration. Serial communication supports I2C with pull-up resistors and SPI with configurable GPIO pins. Output drivers support multiple signaling standards such as LVDS, LP-HCSL, LVPECL, CML, and SSTL with appropriate coupling and termination. Power supply design divides core and output driver voltages, recommending separate power filtering per domain to minimize noise, with options for combined filtering to save PCB space. Detailed reference schematics and power filtering topologies guide optimal design and noise reduction.
Application Note
PLL Loop Filter Design and Fine Tuning
PDF 1.53 MB R31AN0034EU0102 Rev.1.02 Oct 21, 2025
AI-generated Summary: PLL loop filter design involves selecting component values to ensure stable operation and optimized phase noise. The loop bandwidth depends on parameters like charge pump current, VCO gain, and feedback divider. Second and third order passive loop filters are common, with specific calculations for cutoff, zero, and pole frequencies guiding component selection. Proper tuning of loop bandwidth enhances PLL stability and phase noise performance, demonstrated through lab experiments and calculation examples.
Application Note
Choosing a Crystal for VersaClock 7 Devices
PDF 404 KB R31AN0029EU0103 Rev.1.03 Oct 13, 2025
AI-generated Summary: Crystal selection for VersaClock 7 devices requires meeting specific frequency, ESR, load capacitance, and drive level specifications to ensure stable oscillator operation. Recommended crystals range from 8 to 80 MHz, with ESR limits varying by frequency band. A detailed list of acceptable crystals from various manufacturers, including their frequency tolerance, stability, aging, and temperature range, guides optimal crystal choice based on application needs. For example, a 50 MHz crystal suits 100 MHz output clock synthesizers. Frequency tolerance and aging parameters can be customized per application requirements.
Application Note
Choosing the Right Crystal for Clocking Devices
PDF 326 KB R31AN0027EU0101 Rev.1.01 Sep 24, 2025
AI-generated Summary: Selecting the appropriate crystal for clocking devices requires considering parameters such as nominal frequency, frequency tolerance, load capacitance, equivalent series resistance (ESR), operating temperature, drive level, and aging tolerance. Clock synthesizers benefit from crystals with integer-related frequencies to minimize jitter, while jitter attenuators should avoid integer or near-integer frequency ratios to prevent spurs. Higher crystal frequencies improve phase noise performance. Load capacitance affects oscillation frequency and startup reliability, and ESR must meet device specifications to ensure proper operation. Frequency variation combines tolerance, stability, and aging, which must align with application needs. Drive level ratings prevent premature aging and damage.
Application Note
VersaClock 7 (VC7) Internal Capacitance Configuration
PDF 406 KB R31AN0076EU0100 Rev.1.00 May 31, 2024
AI-generated Summary: Internal capacitance within the VersaClock® 7 (VC7) device is configured using Renesas IC Toolbox software (RICBox). Load capacitance on the crystal is calculated by considering internal stray capacitance (fixed at 8.2pF), external stray capacitance from PCB traces, and adjustable trimming capacitance. The trimming capacitance can be set in 0.42pF steps from 0 to 26.46pF. Bench setup for trimming involves using evaluation boards (RC21008/RC21012 EVBs), frequency counters, and RICBox software to measure and adjust the crystal frequency by tuning load capacitance. The document details step-by-step procedures for hardware setup, software configuration, and frequency measurement to optimize crystal trimming for accurate oscillator performance.

View More (16)

Product Notices (PCN, EOL, etc) (4)

Product Change Notice
PCN# : 240019 Add alternate assembly locations on select VFQFPN packages and transfer assembly location on select PLCC package
PDF 1003 KB Nov 20, 2024
Product Change Notice
PCN# : 240002 (R1) VersaClock 7 Family revision update
PDF 225 KB May 20, 2024
Product Change Notice
PCN# : 240002 VersaClock 7 Family revision update
PDF 224 KB Mar 18, 2024
Product Change Notice
PCN# : 220019 Add Alternate Assembly Locations on VFQFPN and FCLGA Packages
PDF 771 KB Jul 22, 2022

Schematics & Design Files (2)

PCB Design Files
RC21008A/RC31008A DSN Symbol File
ZIP 18 KB Aug 05, 2022
PCB Design Files
RC21012A/RC31012A DSN Symbol File
ZIP 657 KB Aug 05, 2022

Marketing Collateral (1)

Overview
VersaClock Family Overview
PDF 379 KB R31DS0004EU0003 Rev.0.03 Oct 23, 2025

Other (2)

Report
RC310xx ITUT-T G.8262, ITU-T G.8262.1 Compliance Report
PDF 3.77 MB R31UZ0006EU0100 Rev.1.00 Dec 18, 2023
Document
VersaClock 7 Schematic Checklist
XLSX 809 KB Jul 29, 2022

Renesas Boards & Kits

RC31008-EVB

Evaluation Kit for VersaClock 7 Programmable Clock

The RC31008A Evaluation Board (EVB) is designed to support users evaluating the RC31008A using clock generation in synthesizer mode for PCIe Gen 1-6 compliance or in jitter attenuation mode. When the EVB is connected via USB to the user’s computer running Renesas Integrated Circuit Toolbox... Read More

Recommended Documents:

RC210xxA/RC310xxA Evaluation Board Manual

Order Now

RC31012-EVB

Evaluation Kit for VersaClock 7 Programmable Clock

The RC31012A Evaluation Board (EVB) is designed to support users evaluating the RC31012A using clock generation in synthesizer mode for PCIe Gen 1-6 compliance or in jitter attenuation mode. When the EVB is connected via USB to the user’s computer running Renesas Integrated Circuit Toolbox... Read More

Recommended Documents:

RC210xxA/RC310xxA Evaluation Board Manual

Order Now

RC21008_31008-PROG

Programming Boards for VersaClock 7 Programmable Clock

The VersaClock^® 7 programmer board is made to ease the programming of RC21008 and RC31008 blank devices. With the onboard USB interface, RICBox™ Graphical User Interface (GUI) can be used to communicate with the blank device in the socket for configuration and programming.

Recommended Documents:

RC21008A/RC31008A Programmer Board Manual

Order Now

RC21012_31012-PROG

Programming Boards for VersaClock 7 Programmable Clock

The VersaClock^® 7 programmer board is made to ease the programming of RC21012 and RC31012 blank devices. With the on-board USB interface, RICBox™ Graphical User Interface (GUI) can be used to communicate with the blank device in the socket for configuration and programming.

Recommended Documents:

RC21012A/RC31012A Programmer Board Manual

Order Now

RCTIMING-DEMO

Renesas Timing Product Demo Kit

RCTIMING-DEMO is a Renesas products combination kit. The kit includes a Renesas RL78 MCU, DA14531MOD, Linear Regulators (LDO), RTC (1338-31DVG) and programmable clock generator VersaClock 7 (VC7) to implement a demo kit to support programming clock generator through laptop or smartphone and... Read More

Recommended Documents:

VersaClock 7 Setup Process for RCTIMING-DEMO Timing Solution

Order Now

Filters

Loading Loading

English

VersaClock 7 Programmable Jitter Attenuator Family

Features

Description

Parameters

Package Options

Applications

Filters

Applied Filters

Recommended Documents (2)

Datasheets (1)

Manuals & Guides (3)

Application Notes & White Papers (16)

Product Notices (PCN, EOL, etc) (4)

No Results Found.

No Results Found.

Schematics & Design Files (2)

No Results Found.

No Results Found.

No Results Found.

Marketing Collateral (1)

Other (2)

No Results Found.

No Results Found.

Renesas Boards & Kits

Filters

Software & Tools

Filter by Type

Filter by Provider

Sample Code

Filter by Application

Filter by Function

Filter by Compiler

Filter by IDE

Simulation Models

Partner Solutions