The Embedded Target for RH850 Multicore is a RH850 model-based multicore environment that simplifies complex driving control for the autonomous-driving era. In addition to the multicore support of the PILS (Note) tool for automatic configuration of environments, Embedded Target for Renesas CS+, it can also be interlinked with a model-based parallelization tool from eSOL Co., Ltd.

In addition, Embedded Target for RH850 Multicore + Multirate can directly and automatically generate parallelized code for multicore devices that are to run code from control models for engines, vehicle bodies and so on, which will, in general, require multiple control periods (requiring multi-rate control).

The Embedded Target for RH850 Multicore generates parallel code for multicore RH850 devices through the implementation phase of a Simulink® model from The MathWorks®, Inc. It contributes to innovative automotive control systems for “eco-cars” (fuel economy and CO2 regulation) and to enhanced safety through the evaluation of functionality and performance in the flow of development.

PILS: Processor In the Loop Simulation



  • This enables evaluation of the operation of systems with multiple control periods, such as systems for controlling engines and bodies, and ECUs (Electronic Control Units), in which multiple systems for controlling various items in the vehicle as a whole are integrated.
    • The generated schedulers are conformant with the type α control model that the MathWorks Automotive Advisory Board (MAAB) recommends in the Control Algorithm Modeling Guidelines.
    • Automatically generated code is of the multi-rate single-task type and runs on multicore devices without an OS.
  • The allowable margins for processing, for which the worst execution timespans during simulation are going to be the control periods, can be checked
    • Graphical display of the states of execution for each core in sub-system units of Simulink models
    • Acquisition of execution times in sub-system units at the time of simulation through the debugger of CS+
    • Graphical display of the states of execution for each core in sub-system units
  • This makes it possible to compare and examine which software structures make effective use of the capacity of the multiple cores directly on MATLAB® and Simulink models
    • Automatically finds the best allocations of cores for complex innovative control systems then parallelizes them
    • Automatically finds the best core allocations for control systems in cooperation with the MBP tool from eSOL Co., Ltd.
  • Returning to earlier stages in design due to incorrect estimation of parallel performance before implementing software can be avoided, and the development times for multicore control software can be shortened
    • Automatically generates parallel source code and provides visualization of the performance of multiple cores during modelling
  • Cycle-accurate simulators as optional features of CS+, which allow the measurement of times that closely reflect those of actual systems. (For some of the RH850 MCUs) [Cycle-Accurate Simulator for RH850]
  • Learn More

new_releasesRelease Information

  • The Embedded Target for RH850, which supports the block unit performance analysis of the single core is also available.
  • To purchase the tool, contact your local Renesas Electronics marketing office or distributor for release date.

Operating Environment

Type of License

Annual license, i.e. a license with a one-year expiry period. Contact your nearest Renesas distributor with regard to purchasing products.


For details of the Target Devices, refer to [Target Devises] at the bottom of this page.


Title language Type Format File Size Date
[Flyer] RH850 Model-Based Development Environment for Multi-Rate Control 日本語 Flyer PDF 803 KB


  • Generation of code for verifying algorithms from Simulink models
  • Automatic generation of Processor in the Loop Simulation (PILS) environments

Flow of Operations

  1. Measuring execution times: The execution times of a Simulink model are measured in sub system units by using the software trace function of the debugger of CS+ on PILS of a single core. (This function is also supported even Embedded Target for RH850.)
  2. Finding the optimal core allocation: A search for the best core allocation based on the execution times acquired in step 1 is conducted through interlinked operation with the optional “eSOL MBP Renesas RH850 MBD Package” (provisional name) of the Model-Based Parallelizer (provisionally referred to as eSOL MBP in this document) from eSOL, and parallelization proceeds.
  3. Code generation: Synchronous processing is automatically allocated among the cores in accord with the core allocation plan from the model-based parallelization tool or an allocation plan specified by the user, and parallel source code for the RH850 is generated by the Embedded Coder from The MathWorks, Inc.
  4. Re-measuring execution time: The execution times with the cores having been allocated in sub-system units are acquired by the debugger function of CS+, and the states of execution for each core are displayed in a graph.

Comparison of the Functions of Embedded Target Products

PIL Simulation on Single-Core Products (Supports multi-rate control) PIL Simulation on Multicore Products Load Module Generation by GHS Compiler Performance Analysis in Blocks Interlinking with eMBP
One Core Used Multiple Cores Used
License Type Embedded Target for RH850 Multicore + Multirate
- RH850 multicore multirate version
lens lens
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Embedded Target for RH850 Multicore
- RH850 multicore version
lens lens lens lens lens lens
Embedded Target for RH850
- RH850 single-core version
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lens Supported | — Not supported

1. Supports multi-rate control
2. Support for multi-rate control is in planning.

Target Devices

Embedded Target for RH850 Multicore + Multirate and Embedded Target for RH850 Multicore support the MCUs listed below.

Contact our distributors regarding our plans in regard to support for the other MCUs, i.e. those for which we do not currently provide a cycle-accurate simulator.

Series Applicable MCU Cycle-accurate simulator
RH850/C1x RH850/C1H Yes
RH850/C1x-A RH850/C1M-Ax (Note1) Please contact us.
RH850/E1x RH850/E1M-S2 (Note2) Please contact us.
RH850/F1x RH850/F1L, RH850/F1K, RH850/F1KM, RH850/F1H Under planning
RH850/P1x-C RH850/P1H-C, RH850/P1M-C Yes
RH850/P1x RH850/P1M-E Please contact us.
RH850/E2x RH850/E2M Yes
  1. Scheduled to be supported in November 2021.
  2. Use only main CPU.


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