1. Sophisticated Architecture for Embedded Systems
The need for increasing added value and system complexity demands higher microcontroller performance. At the same time, energy saving and longer battery life is also needed, so lower power consumption is also demanded. The RX core continues to evolve even further to meet these demands.
Comparison of RXv 1 core, RXv 2 core, RXv 3 core
|Architecture||32-bit CISC, Harvard architecture|
|General purpose registers||32bit × 16ch|
|Compatibility||RXv1||Downward compatible with RXv1||Downward compatible with RXv1/RXv2|
|Instruction set||90 instructions||109 instructions
(90 RXv1 instructions + 19 instructions)
(109 RXv2 instructions + 4 instructions)
|Pipeline||5-stage||Improved 5-stage pipeline
Improved IPC through enhanced pipeline
(enhanced performance through parallel execution of memory access and operations)
|Improved 5-stage pipeline
Improved IPC through enhanced pipeline
(enhanced performance through improved combination of simultaneously executable instructions)
|DSP function instructions||Single-cycle MAC instructions(16-bit), Accumulator × 1||Single-cycle MAC instructions (16-bit, 32-bit), Accumulator × 2||Same as on the left|
|FPU||Single-precision floating-point operation instruction||Same as on the left||Single precision / double precision floating-point operation instruction (double precision is optional)|
|Performance||Up to 3.12 CoreMark/MHz||Up to 4.55 CoreMark/MHz||Up to 5.8 CoreMark/MHz|
|Others||-||-||Register bank save function (optional)
*Availability of optional functions depends on product specifications
Note: 1. Value current as of date of issue.
New-generation CPU that inherits the strengths of its predecessors
The RX core combines the strengths of the CISC architecture of the H8S, H8SX, M16C, and R32C Families and the agility of the RISC architecture of the SuperH Family.
32-bit class operation performance with 16-bit class code size
The RXv2 core has an enhanced instruction set, DSP/FPU instructions, and pipeline, improving processing performance per cycle. In addition to further enhancements to instruction set and pipeline, RXv3 adds a register save bank, improving CPU register set save/return speed and real-time control performance. RX cores address demands for more system complexity and added value for end products.
* The CoreMark score is the published value published in EEMBC
2. Overwhelming Power Performance
Fast interrupt response performance
Interrupt response performance and standby time are substantially improved by the use of technologies developed for earlier products, such as high-speed flash memory that enables zero-wait access, and optimized register assignment.
Excellent power efficiency: improved operating performance and reduced power consumption
The unique RX CPU core combines a design optimized for power efficiency and an exclusive fabrication process to achieve excellent operation performance and low power consumption.
Better code efficiency
Using the dedicated instructions of the RX core and a Renesas compiler can bring out 100% of the core's capability and program size can be reduced by 30%.
3. Comprehensive Lineup
Comprehensive peripheral functions
RX microcontrollers are equipped with peripheral functions for various applications, such as connectivity functions such as Ethernet, USB, and CAN, HMI functions such as touch sensor and LCD, an advanced timer for motor control, and 12-bit high-speed A/D converter.
Comprehensive pin/memory lineup
RX microcontrollers are available in a comprehensive pin count and memory lineup. RX microcontrollers can satisfy the requirements of a wide range of different applications.
Hardware safety functions
The RX Family features hardware implementation of system safety functions, greatly reducing the load imposed by software. These safety functions can be used to build electric home appliances that comply with the IEC 60730 Class B safety standard and industrial equipment that complies with the IEC 61508 safety standard.
|Function||Safety functions that use this function|
|CPU||Independent watchdog timer (IWDT)||CPU runaway detection using WDT based on clock other than CPU clock|
|Clock||Oscillation-stop detection||Oscillation-stop detection|
|Clock frequency accuracy
measurement function (CAC)
Frequency measurement function (MCK)
|Clock frequency error detection|
|Data operation circuit (DOC)||Circuit to assist memory checking|
|CRC calculation circuit (CRC)||Memory error detection|
|Serial||Communication data error detection|
|A/D||A/D self-diagnostics||A/D converter unit error detection|
|A/D disconnection detection||Analog input disconnection detection assist|
|Pins||Port output enable (POE)||Protection of pins from overcurrent|
Anticipating the IoT era, RX microcontrollers have built-in encryption functions to protect devices against eavesdropping and entry and execution of viruses. Products with built-in trusted secure IP with even more robust key management for higher level of safety are also available.
4. Existing Products and RX Extensibility
Extensibility and scalability
The RX Family is designed to maintain compatibility between the CPU instructions, pin assignments, and functions of the various product versions. The instruction set of the RXv2 core is downward compatible with the instruction set of the RXv1 core.
The RX Family covers with a single CPU core the performance ranges of a variety of existing CPU cores. This makes software reusability and the use of common development tools possible. The RX Family offers seamless deployment from the bottom to the top of the product line.
5. Easy and Comfortable Development
A comprehensive development environment that provides end-to-end support from initial evaluation to development and mass production
Drivers, middleware, and sample software
Renesas offers comprehensive tools that shorten development time, such as a tool that automatically generates drivers.