Clocks & Timing

Overview

The 5P49V6968 is a member of IDT's VersaClock® 6E programmable clock generator family. The 5P49V6968 is intended for high-performance consumer, networking, industrial, computing, and data-communications applications. The reference clock can come from one of the two redundant clock inputs. A glitchless manual switchover function allows one of the redundant clocks to be selected during normal operation.
 
Configurations may be stored in on-chip One-Time Programmable (OTP) memory or changed using I²C interface.
 
5P49V6968 - Block Diagram
5P49V6968 - Pinout
5P49V6968 - Block Diagram
5P49V6968 - Pinout
  • < 100mW core power (at 3.3V)
  • < 0.5ps RMS phase jitter (typical)
  • PCIe Gen 1/2/3/4/5 spread spectrum off
  • PCIe Gen 1/2/3/4 spread spectrum on
  • 1/10GbE, USB 3.0
  • 3 universal outputs pairs: LVPECL, LVDS, HCSL, or 6 LVCMOS outputs
  • 3 independent frequencies with 0.001MHz–350MHz output range
  • 8 additional copies of LP-HCSL outputs (1 independent frequency)
  • Reference output
  • 1.8V / 2.5V / 3.3V core and output voltages
  • 2 programmable I²C addresses allowing multiple devices to be used in same system
  • Up to 4 different configuration sets in OTP non-volatile memory
  • Supported by IDT Timing Commander™  software tool
  • Quick sampling and customization process supported by online-form submission
  • 6 x 6 mm 48-VFQFPN package
  • -40°C to +85°C operating temperature range
5P49V6968 5P49V6965 5P49V6967 5P49V6975
Inputs (#) 2 2 2 1
Outputs (#) 11 5 9 5
Output Type HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL HCSL, LVCMOS, LVDS, LVPECL HCSL, LP-HCSL, LVCMOS, LVDS, LVPECL HCSL, LVCMOS, LVDS, LVPECL
Phase Jitter Typ RMS (ps) 0.500 0.500 0.500 0.500
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Documentation

Title Type Date
5P49V6968 Datasheet
PDF1.08 MB
Datasheet
IDT Products for Wired Broadband Applications
PDF686 KB
Application Brief
Timing Commander Installation Guide
PDF348 KB
Application Note
PCB Layout Considerations for Designing VersaClock Clock Generator Family
PDF1.17 MB
Application Note
How to Make 1.2V LVCMOS from 1.8V LVCMOS Output
PDF256 KB
Application Note
AN-1014 Microstrip vs Stripline: Crosstalk and RMS Phase Jitter
PDF486 KB
Application Note
AN-975 Cascading PLLs
PDF255 KB
Application Note
AN-970 Glitchless Frequency Adjustment using Fractional Output Divider
PDF717 KB
Application Note
AN-954 Layout and EMI Recommendations for Automotive Applications
PDF406 KB
Application Note
AN-960 Layout and EMI Recommendations for Automotive Applications (short form)
PDF342 KB
Application Note
AN-918 Programmable Clocks vs Crystal Oscillators
PDF307 KB
Application Note
AN-905 Using VersaClock® 6 as Reference Clock for Xilinx® Series 7 FPGAs
PDF188 KB
Application Note
AN-844 Termination - AC Coupling Clock Receivers
PDF170 KB
Application Note
AN-845 Termination - LVCMOS
PDF146 KB
Application Note
AN-846 Termination - LVDS
PDF133 KB
Application Note
AN-842 Thermal Considerations in Package Design and Selection
PDF495 KB
Application Note
AN-815 Understanding Jitter Units
PDF565 KB
Application Note
AN-806 Power Supply Noise Rejection
PDF438 KB
Application Note
AN-808 PCI Express/HCSL Termination
PDF137 KB
Application Note
VersaClock 6E Family Register Descriptions and Programming Guide
PDF990 KB
Manual - Development Tools
VersaClock Family Overview
PDF392 KB
Overview
PCI Express Timing Solutions Overview
PDF2.40 MB
Overview
IDT Clock Generation Overview
PDF1.83 MB
Overview
PCN# : 210023 Add Alternate Assembly Locations on Select VFQFN Packages
PDF726 KB
Product Change Notice
IDT Clocks for Xilinx Ultrascale FPGAs
PDF256 KB
Technical Brief
IDT Clocks for Altera's Stratix V and Arria V/X FPGAs
PDF238 KB
Technical Brief

Design & Development

Software Downloads

Title Type Date
VersaClock 6E Timing Commander Personality File v1.4.1
ZIP5.88 MB
Software & Tools - Other
Timing Commander Installer (v1.17)
ZIP18.02 MB
Software & Tools - Other

Boards & Kits

5P49V6968 - Evaluation Board (top)

5P49V6968-EVK

Evaluation
Order Now

Evaluation Board for 5P49V6968 VersaClock® 6E

This is the evaluation board for the IDT 5P49V6968 VersaClock 6E programmable clock generator. With RMS phase jitter of less than 0.5ps over the full 12kHz to 20MHz...
Featured Documents:
5P49V6967 and 5P49V6968 Evaluation Board Manual

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on products in the Product Options table. If a symbol or model isn't available, it can be requested directly from the website.

Explore ECAD Models

Models

Title Type Date
5P49V6968 IBIS Model
ZIP333 KB
Model - IBIS

Product Options

This device is factory-configurable. Try the Custom Part Configuration Utility.
    Processing table
    Part Number
    Pkg. Type
    Lead Count (#)
    Temp. Grade
    Pb (Lead) Free
    Carrier Type
    Buy / Sample
    5P49V6968A000NDGI
    play_circleActive
    memory
    view_in_ar
    Samples Available
    		 VFQFPN 48 I Yes Tray Get Samples,
    5P49V6968A000NDGI8
    play_circleActive
    memory
    view_in_ar
    		VFQFPN 48 I Yes Reel
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    Support

    Contact Technical Support
    Customize Part
    Get Samples
    Clocks & Timing FAQs
    Clocks & Timing Forum
    Contact a Sales Representative
    VersaClock® 6E - High-performance Programmable Clock Generator

    The VersaClock® 6E programmable clock generator devices offer a combination of low power, flexibility and performance for a wide range of applications. These features make it ideal for simplifying system design by replacing multiple discrete timing components and reducing bill of materials (BOM). The VersaClock 6E supports operating voltages from 1.8 to 3.3 V, differential (LVPECL/HCSL/LVDS/LP-HCSL) and LVCMOS output types, and fractional dividers to accurately generate virtually any frequency. Products satisfy system requirements from oscillator replacement to PCIe® Gen 1/2/3 and to communications applications, while consuming very little power.

    For more information about VersaClock 6E, visit https://www.idt.com/versaclock.

    Video List
    VersaClock® 6E - High-performance Programmable Clock Generator
    VersaClock® 6 Product Overview - Low Jitter Programmable Clock Generator
    IDT Timing Commander™ Software Overview
    Introduction to Timing Commander™ Software Tool by IDT
    IDT Timing Commander
    IDT Timing Solutions for NXP QorIQ / Layerscape CPU
    Overview of Timing Requirements for NXP QorIQ LS Processors

    News & Blog Posts

    Faster Timing Design and Accurate Performance Testing with Jitter Measurement Utility Blog Post Jun 14, 2019
    IDT Expands Award-Winning VersaClock Family of Programmable Clock Generators with New VersaClock 6E News Jan 23, 2018