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型名
説明
ブロック図
状態
Protocol
Function
Process
Data Rate (Mbps)
Interface
Number of Channels
Input Freq (MHz)
Supply Voltage Range (V)
AT40FUS20002
NEW
データシート
LVDSIO000X
NEW
データシート
IP/ETHTSNSW
NEW
データシート
IP/ETHTSNES
NEW
データシート
IP/ETHAVBES
NEW
データシート
URL78HRCN008
NEW
データシート
UCIAPRCN0140
NEW
データシート
IP/PCIE5CTL
NEW
データシート
MIPI DSI-2 Transmitter IP Core
アクティブ
MIPI
Controller, Transmitter
Soft macro
80 to 4500
AMBA® APB, AXI, PPI, Video
—
—
—
MIPI CSI-2 Receiver IP Core
アクティブ
MIPI
Controller, Receiver
Soft macro
80 to 4500
AMBA® APB, CSI-2, DSI, PPI, Video
—
—
—
MIPI D-PHY Transceiver for CSI-2/DSI IP (TSMC 22nm ULL)
アクティブ
MIPI
D-PHY, Transceiver
Soft macro & TSMC 22nm ULL
1200
CSI-2, DSI, PPI
2
—
Core: 1.1V, I/O: 1.8 and 3.3V
MIPI D-PHY Transceiver for CSI-2/DSI IP (Samsung 28nm FD-SOI)
アクティブ
MIPI
D-PHY, Transceiver
Soft macro & Samsung 28nm
1500
CSI-2, DSI, PPI
4
—
Core: 1.1V, I/O: 1.8V
MIPI D-PHY Transceiver for CSI-2/DSI IP (TSMC 40nm LP)
アクティブ
MIPI
D-PHY, Transceiver
Soft macro & TSMC 40nm LP
1000
CSI-2, DSI, PPI
2
—
Core: 1.1V, I/O: 1.8V
MIPI D-PHY Receiver for CSI-2 IP (TSMC 22nm ULP)
アクティブ
MIPI
D-PHY, Receiver
Soft macro & TSMC 22nm ULP
1500
CSI-2, PPI
4
—
Core: 0.9V, I/O: 1.8V
MIPI D-PHY Transmitter for DSI with FPD-Link IP (TSMC 22nm ULP)
アクティブ
FPD-Link, MIPI
D-PHY, Transmitter
Soft macro & TSMC 22nm ULP
FPD-Link: 609, MIPI: 1500
FPD-Link, LVDS, PPI
4
—
Core: 1.0V, I/O: 1.8V
USB 2.0 Full-Speed Transceiver IP
アクティブ
USB 2.0 FS
PHY, Transceiver
TSMC 22nm ULL
1.5, 12
—
1
—
Core: 1.1V, I/O: 3.3V
USB 2.0 PHY for Single-Port Transceiver IP (TSMC 22nm ULL)
アクティブ
USB 2.0
PHY, Transceiver
TSMC 22nm ULL
1.5, 12, 480
UTMI+
1
48, 24, 20, 12
Core: 1.1V, I/O: 3.3V
USB 2.0 PHY for Single-Port Transceiver IP (TSMC 40nm LP)
アクティブ
USB 2.0
PHY, Transceiver
TSMC 40nm LP
1.5, 12, 480
UTMI+
1
48, 24, 20, 12
Core: 1.1V, I/O: 3.3V
USB 2.0 PHY for Multi-Port Transceiver IP (Samsung 28nm FD SOI 8M)
アクティブ
USB 2.0
PHY, Transceiver
Samsung 28nm FD SOI
1.5, 12, 480
UTMI+
1 or 2 ports
48, 30, 24, 20
Core: 1.1V, I/O: 1.8 and 3.3V
USB 2.0 PHY for Multi-Port Transceiver IP (TSMC 28nm HPC+)
アクティブ
USB 2.0
PHY, Transceiver
TSMC 28nm HPC+
1.5, 12, 480
UTMI+ Level 3
1, 2, 3, 4 lanes
48, 30, 24, 20
Core: 0.90 or 1.0V, I/O: 1.8 and 3.3V
SerDes PHY Up to 5Gbps IP
アクティブ
PCIe 2.1, USB 3.0
PHY
TSMC 28nm HPC+
—
PIPE
1, 2, 4, 8 lanes
—
Core: 0.90 or 1.0V, I/O: 1.8V
LVDS I/O Buffer IP
アクティブ
LVDS
I/O buffer
TSMC 16, 22, 28, 40nm, and Samsung 14nm
600 to 1000
LVDS
1
—
1.8 ± 0.15
Flat Panel Display Link Transmitter IP (TSMC 22nm ULP)
アクティブ
FPD-Link
Transmitter
TSMC 22nm ULP
525
LVDS
5
75
Core: 0.9V, I/O: 1.8V
Flat Panel Display Link Transmitter IP (TSMC 28nm HPC)
アクティブ
FPD-Link
Transmitter
TSMC 28nm HPC
1050
LVDS
5
75
Core: 1.0V, I/O: 1.8V
Flat Panel Display Link Receiver IP (TSMC 22nm ULP)
アクティブ
FPD-Link
Receiver
TSMC 22nm ULP
595
LVDS
5
85
Core: 0.9V, I/O: 1.8V
Flat Panel Display Link Receiver IP (TSMC 28nm HPC+)
アクティブ
FPD-Link
Receiver
TSMC 28nm HPC+
500
LVDS
5
71.5
Core: 1.0V, I/O: 1.8V
Ethernet Time-Sensitive Networking Layer 2/3 Switch IP
アクティブ
Ethernet TSN
TSN Switch
Soft macro
10 to 2500
AMBA® APB, AXI
—
—
—
Ethernet Time-Sensitive Networking End Station IP
アクティブ
Ethernet TSN
End Station
Soft macro
10, 100, 1000
AMBA® APB, AXI
—
—
—
Ethernet Audio Video Bridging End Station IP
アクティブ
Ethernet AVB
End Station
Soft macro
100, 1000
AMBA® APB, AXI
—
—
—
PCI Express 5.0 Link Controller IP
アクティブ
PCIe 5
Controller
Soft macro
32GT/s (PCIe 5)
AMBA® AXI, PIPE 5.2
1 lane
—
—
全て選択
型名
Enabled
型名
説明
Enabled
説明
状態
Enabled
状態
Protocol
Enabled
Protocol
Function
Enabled
Function
Process
Enabled
Process
Data Rate (Mbps)
Enabled
Data Rate (Mbps)
Interface
Enabled
Interface
Number of Channels
Enabled
Number of Channels
Input Freq (MHz)
Enabled
Input Freq (MHz)
Supply Voltage Range (V)
Enabled
Supply Voltage Range (V)
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