特長
- MIPI® D-PHY™ Transmitter can be used for an analog driver for the following interfaces:
- MIPI Alliance Specification for D-PHY Version 2.1 15 December 2016
- MIPI Alliance Specification for Display Serial Interface (DSI)
- LVDS Transmitter can be used for an analog driver for the following interfaces:
- FPD-Link (LVDS) Specification for Version D-PHY ANSI/TIA/EIA-644-A FEBRUARY 2001
- Technology is TSMC's 22nm ULP (Ultra-Low Power) 1p10M
- Supply voltage can be applied - 1.0V for core voltage, 1.8V for I/O voltage
- Maximum data rate of each channel is 1.5Gbps at High-Speed mode for the MIPI D-PHY Transmitter
- Data rate of each channel is 609Mbps for FPD-Link (LVDS)
MIPI D-PHY Transmitter for DSI with FPD-Link IP (TSMC 22nm ULP) Block Diagram
説明
Renesas' MIPI® D-PHY™ and FPD-Link (LVDS) combinational transmitter is a useful 4-channel driver hard macro for Display Serial Interface (DSI), fabricated using TSMC's 22nm ULP (Ultra-Low Power) process.
パラメータ
| 属性 | 値 |
|---|---|
| Protocol | MIPI, FPD-Link |
| Function | D-PHY, Transmitter |
| Process | Soft macro & TSMC 22nm ULP |
| Data Rate (Mbps) | MIPI: 1500, FPD-Link: 609 |
| Interface | LVDS, PPI, FPD-Link |
| Number of Channels | 4 |
| Supply Voltage Range (V) | Core: 1.0V, I/O: 1.8V |
