特長
- Used for an analog transceiver (Tx) with the following interfaces
- PCI Express® 2.1 (compliant with PCI-Express Base Specification Revision 2.1)*1
- USB 3.0 SuperSpeed® (compliant with Universal Serial Bus 3.0 Specification Revision 1.0)*1
- PCI Express 2.1 and USB 3.0 SuperSpeed can be used as a combination macro*1
- Multi-lane support for PCI Express 2.1 (1, 2, 4, and 8 lanes available)
- Technology is TSMC 28nm HPC+ (High-Performance Compact Plus) 1p10M
- Supply voltage can be applied - 0.90V for nominal and 1.0V for overdrive of core voltage, 1.8V for I/O voltage
- Selectable 10-bit/20-bit for parallel side interface
- 2-tap FIR filter for Tx equalizer/Tunable peaking amplifier for Rx equalizer
- Built-in differential input buffer for a clean reference clock
SerDes PHY Up to 5Gbps IP Block Diagram
説明
Renesas' SerDes PHY IP, a useful analog transceiver hard macro for various high-speed serial interfaces, is fabricated using TSMC's 28nm HPC+ (High-Performance Compact Plus) process technology. This macro is designed for PCI Express® 2.1 and USB 3.0 SuperSpeed®.
*1: There are some restrictions on the use cases of PCI Express 2.1 and USB 3.0 SuperSpeed. Please contact us for detailed information before purchasing the product.
パラメータ
| 属性 | 値 |
|---|---|
| Protocol | PCIe 2.1, USB 3.0 |
| Function | PHY |
| Process | TSMC 28nm HPC+ |
| Interface | PIPE |
| Number of Channels | 1, 2, 4, 8 lanes |
| Supply Voltage Range (V) | Core: 0.90 or 1.0V, I/O: 1.8V |
