特長
- Tx/Rx
- Input/Output pins of the CAN module
- Protocol controller
- Handles CAN protocol processing such as bus arbitration, bit timing at transmission and reception, stuffing, error handling, etc.
- Acceptance filter
- Performs filtering of received messages. The entries in the Acceptance filter list RAM are used for the filtering process.
- Two timers
- Reception timestamp function
- Transmission separation time for First In, First Out (FIFO) buffers
- Acceptance Filter List RAM
- This RAM is used to store message acceptance filtering entries for all channels. Each acceptance filter entry has an individual ID, data length code, payload data, a message pointer for an upper-layer application usage, and a message direction pointer. The Acceptance Filter List RAM (AFLRAM) is divided into two parts to accelerate the AFL access process.
- Message Buffer RAM
- This RAM is used to store messages for reception and for transmission using a normal message buffer or a FIFO buffer. Each message entry has an individual ID, data length code, payload data, a message pointer for an upper-layer application usage, and a time stamp.
Multi-Channel CAN FD Controller IP Block Diagram
説明
Renesas' Multi-Channel CAN FD Controller IP can be used to embed multiple CAN channels (2, 4, 6, and 8-channel versions are available). Each CAN channel can be configured to CAN FD or classic CAN and transmit and receive both message formats: the standard identifier (ID), which is 11 bits, and the 29-bit extended ID. This IP is compliant with ISO 11898-1 (2015) specifications.
パラメータ
| 属性 | 値 |
|---|---|
| Protocol | CAN FD |
| Function | Controller |
| Process | Soft macro |
| Interface | AMBA® APB |
| Number of Channels | 2, 4, 6, or 8 |
