特長
- Can be used for an analog transmitter/receiver for the following interfaces:
- MIPI Alliance Specification for D-PHY Version 2.1 15 December 2016
- MIPI Alliance Specification for DSI (Display Serial Interface)
- MIPI Alliance Specification for CSI-2 (Camera Serial Interface 2)
- Technology is TSMC's 40nm Low Power (LP) 1p6M.
- Supply voltage can be applied - 1.1V for core voltage, 1.8V for I/O voltage
- Maximum data rate of each channel is 1.0Gbps in High-Speed mode
説明
Renesas MIPI® D-PHY™ Transmitter/Receiver IP is a 2 data lanes transmitter/receiver hard macro for DSI℠/CSI-2®, fabricated using TSMC's 40nm Low Power (LP) process.
パラメータ
| 属性 | 値 |
|---|---|
| Protocol | MIPI |
| Function | D-PHY, Transceiver |
| Process | Soft macro & TSMC 40nm LP |
| Data Rate (Mbps) | 1000 |
| Interface | CSI-2, DSI, PPI |
| Number of Channels | 2 |
| Supply Voltage Range (V) | Core: 1.1V, I/O: 1.8V |