Features
- Absolute Maximum Ratings
- Supply voltage Vcc: 24V
- Junction temperature Tj: –40°C to +150°C
- Electrical characteristics
- UVLO operation start voltage VH: 12V ± 0.8V
- UVLO operation shutdown voltage VL: 9.2V ± 0.7V
- UVLO hysteresis voltage Hysuvl: 2.8V ± 0.7V
- Functions
- Boost converter control with critical conduction mode
- Two mode overvoltage protection
- Mode 1: Dynamic OVP corresponding to a voltage rise by load change
- Mode 2: Static OVP corresponding to overvoltage in stable.
- Feedback loop open detection
- Overcurrent protection
- Dynamic UVP corresponding to a voltage fall by load change
- Off Time Control function (Frequency Limiter)
- Package lineup: Pb-free SOP-8 (JEDEC)
Description
The R2A20113A controls a boost converter to provide an active power factor correction. The R2A20113A adopts critical conduction mode for power factor correction and realizes high efficiency and a low switching noise by zero current switching. Because the zero current is detected by using the GND current, the ZCD Auxiliary winding is unnecessary. The feedback loop open detection, two mode overvoltage protection, overcurrent protection are built in the R2A20113A, and can constitute a power supply system of high reliability with few external parts.
Parameters
| Attributes | Value |
|---|---|
| UVLO Rising (V) | 12 |
| UVLO Falling (V) | 9.2 |
| Output Per Driver UGATE Source|Sink | .020 | .020 |
| Supply Current Icc (µA) | 1800 |
| Function | DUVP, Off Time control |
| Remarks | CRM Single PFC |
| Icc (Typical) (mA) | 1.7 |
| Tstg (Min) (°C) | -55 |
| Tstg (Max) (°C) | 150 |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) |
|---|---|---|
| SOP | 5 x 4 x 1.75 | 8 |
Application Block Diagrams
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Datasheet
| Part Number | Status | Samples | Stock | RoHS | Package | Budgetary Price (USD) | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Pb (Lead) Free | Country of Assembly | Country of Wafer Fabrication |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| R2A20113ASP#W5 | Active | Available | In Stock | Contact | SOP | 1ku | $0.51 | 8# | Embossed Tape | 1 | Yes | PHILIPPINES | JAPAN |
| R2A20113ASP#W0 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | SOP | 8# | Embossed Tape | Yes |
Complete Your Design
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READ2304G
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Datasheet
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- Application NotePDF 1.3 MB R19AN0015ED0102 Rev.1.02 Jul 01, 2013AI-generated Summary: The document provides layout recommendations and design rules for a dual port Ethernet PHY device supporting 10Base-T, 100Base-TX, and 100Base-FX. It covers strap pin configuration options for initial start-up settings, detailing the use of pull-up and pull-down resistors, including recommended resistor values and schematic examples. The strap pins function only during power-up or reset, with internal and external resistor configurations advised for noise immunity. Additional chapters address media interfaces, power supply layout, clock input, LED control, and unused pins.
- Application NotePDF 1.21 MB R19AN0014ED0102 Rev.1.02 Jul 01, 2013AI-generated Summary: The document provides layout recommendations and design rules for Dual PHY and Single Channel PHY ASSP devices. It covers strap pin configuration options for initial start-up settings, including pull-up and pull-down resistor values and configurations to ensure stable operation in noisy environments. The layout guidelines include power supply design, differential pair routing, media-dependent interfaces, MAC interfaces, and clock input circuits. Examples and tables illustrate resistor values and schematic configurations for strap pins.
- Application NotePDF 224 KB R03AN0009EJ0100 Rev.1.00 Feb 22, 2012AI-generated Summary: The document explains the internal functions of the R2A20112A IC, focusing on its UVLO block which prevents operation under low voltage, and the 5 V reference voltage used internally. It details the Error Amplifier that stabilizes PFC output voltage, the Zero Current Detection circuit essential for CRM operation, and the RAMP generator that controls PWM ON time using external components. The drive stage outputs pulses to power MOSFETs with specific peak current capabilities and includes driver circuit examples for different MOSFET gate charges.
- Application NoteAI-generated Summary: The built-in oscillator frequency depends on an external resistor and a 10 pF capacitor, with a maximum 50% duty cycle at 48 kHz. The oscillator charges and discharges the capacitor between 0.2 V and 2 V. The error amplifier uses a transconductance amplifier to regulate output based on feedback voltage. The output pin drives an external MOSFET with up to 900 mA peak current. The peak current control circuit maintains constant inductor current using overcurrent protection via the CS pin. The constant ON time control uses feedback from the FB pin to regulate inductor current, adjusting peak current proportionally to input voltage for power factor correction.
- Application NoteAI-generated Summary: The RAMP slope inside the chip depends on the external resistor RRT and an internal 10-pF capacitor, controlling the MOSFET ON time based on error amplifier voltage and zero current detection. The output stage features a single totem-pole driver capable of ±900 mA peak current, enabling direct MOSFET driving with adjustable drivability. Protection functions include static and dynamic overvoltage, feedback low detection, overcurrent protection via an external sense resistor, and off-time control to limit switching frequency and improve efficiency during light loads.
- Application NotePDF 397 KB an1684 Jan 19, 2004AI-generated Summary: The document outlines important legal disclaimers and usage guidelines for semiconductor products. It emphasizes user responsibility for product design and safety, disclaims liability for damages, and clarifies no intellectual property licenses are granted. Products are categorized by quality grades with specific application recommendations. Users must comply with laws, avoid unauthorized modifications, and ensure safe use within specified conditions. Contact details for Renesas Electronics sales offices worldwide are provided.
- Application NotePDF 509 KB an1681 Jan 19, 2004AI-generated Summary: The document explains grounding techniques for PCB layouts using a dual op amp example on a single-layer copper board. It compares three grounding schemes: a center spine ground trace, an outer ground plane, and a split/star ground plane, highlighting the benefits of single-point grounding to minimize noise and antenna effects. It emphasizes following current paths, minimizing loop lengths, and ensuring close forward and return paths to reduce interference. The document also includes disclaimers on product use, quality grades, safety, and legal compliance.
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- Application NotePDF 1.3 MB R19AN0015ED0102 Rev.1.02 Jul 01, 2013AI-generated Summary: The document provides layout recommendations and design rules for a dual port Ethernet PHY device supporting 10Base-T, 100Base-TX, and 100Base-FX. It covers strap pin configuration options for initial start-up settings, detailing the use of pull-up and pull-down resistors, including recommended resistor values and schematic examples. The strap pins function only during power-up or reset, with internal and external resistor configurations advised for noise immunity. Additional chapters address media interfaces, power supply layout, clock input, LED control, and unused pins.
- Application NotePDF 1.21 MB R19AN0014ED0102 Rev.1.02 Jul 01, 2013AI-generated Summary: The document provides layout recommendations and design rules for Dual PHY and Single Channel PHY ASSP devices. It covers strap pin configuration options for initial start-up settings, including pull-up and pull-down resistor values and configurations to ensure stable operation in noisy environments. The layout guidelines include power supply design, differential pair routing, media-dependent interfaces, MAC interfaces, and clock input circuits. Examples and tables illustrate resistor values and schematic configurations for strap pins.
- Application NotePDF 224 KB R03AN0009EJ0100 Rev.1.00 Feb 22, 2012AI-generated Summary: The document explains the internal functions of the R2A20112A IC, focusing on its UVLO block which prevents operation under low voltage, and the 5 V reference voltage used internally. It details the Error Amplifier that stabilizes PFC output voltage, the Zero Current Detection circuit essential for CRM operation, and the RAMP generator that controls PWM ON time using external components. The drive stage outputs pulses to power MOSFETs with specific peak current capabilities and includes driver circuit examples for different MOSFET gate charges.
- Application NoteAI-generated Summary: The built-in oscillator frequency depends on an external resistor and a 10 pF capacitor, with a maximum 50% duty cycle at 48 kHz. The oscillator charges and discharges the capacitor between 0.2 V and 2 V. The error amplifier uses a transconductance amplifier to regulate output based on feedback voltage. The output pin drives an external MOSFET with up to 900 mA peak current. The peak current control circuit maintains constant inductor current using overcurrent protection via the CS pin. The constant ON time control uses feedback from the FB pin to regulate inductor current, adjusting peak current proportionally to input voltage for power factor correction.
- Application NoteAI-generated Summary: The RAMP slope inside the chip depends on the external resistor RRT and an internal 10-pF capacitor, controlling the MOSFET ON time based on error amplifier voltage and zero current detection. The output stage features a single totem-pole driver capable of ±900 mA peak current, enabling direct MOSFET driving with adjustable drivability. Protection functions include static and dynamic overvoltage, feedback low detection, overcurrent protection via an external sense resistor, and off-time control to limit switching frequency and improve efficiency during light loads.View More (7)
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