Features
- VIN_Bulk input supply range: 4.25V to 15.0V
- VIN_Mgmt input supply range: 3.0V to 3.6V
- Four step-down switching regulators: SWA, SWB, SWC, and SWD
- Programmable dual phase and single phase regulator for SWA and SWB
- 3 LDO regulators: VBias, VOUT_1.8V, VOUT_1.0V
- Automatic switchover from VIN_Mgmt input supply to VIN_Bulk input supply
- Independently programmable output voltages, power up and power down sequence for switch regulators
- Input and output power good status reporting mechanism
- VIN_Bulk input supply protection feature: input over voltage
- Multi-time programmable non-volatile memory
- Programmable and DIMM specific registers for customization
- General Status Interrupt function
- Flexible Open Drain IO (3.3V, 2.5V, 1.8V or 1.2V or 1.1V) or Push-Pull IO (1.2V or 1.1V) support
P8900 - Block Diagram
Description
The P8900 PMIC is a power management IC (PMIC) designed for typical DDR5 RDIMM, DDR5 LRDIMM, and DDR5 NVDIMM applications. The PMIC features four step-down switching regulators and three LDO regulators. The P8900 PMIC is designed to support up to 15 Watts of power. It is powered from VIN_Bulk input for switching regulators and VIN_Mgmt input for the rest of the PMIC. The P8900 PMIC supports selectable interface (I²C or I³C) to fit various application environments.
Parameters
| Attributes | Value |
|---|---|
| Qualification Level | Standard |
| Product Type | Power Management IC |
| Processor Supplier | Renesas |
| Total step-down DC/DC converter channels (#) | 2 |
| Step-up DC/DC converter Channels (#) | 0 |
| Input Voltage (Min) (V) | 3 |
| Input Voltage (Max) (V) | 3.6 |
| Bus Voltage (Max) (V) | 15 |
| Output Current Max (A) | 5 |
| Outputs (#) | 4 |
| Function | DDR5 Server PMIC |
| Comm. Interface | I2C, I3C |
| Battery Interface | No |
| GPIOs (#) | 0 |
| Integrated Battery Charger | No |
| Switching Frequency (MHz) | 12.5 - 12.5 |
Package Options
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| FCQFN | 5.0 x 5.0 x 0.9 | 36 | 0.4 |
Application Block Diagrams
 | AMD 4th-Gen EPYC (Genoa) Power & Timing System Complete power and timing system for AMD Genoa with SVI3, DDR5, and PCIe Gen 5/6 support. |
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