特長
- Compliant with Specification for Display Serial Interface 2 (DSI-2) Version 1.1.
- Compliant with PHY Protocol Interface (PPI) to D-PHY™ Version 2.1.
- Compliant with AMBA® APB Protocol Version 2.0.
- Support PPI interface for D-PHY physical layer option
- Supports De-facto standard interface for video transmission (video interface)
- Pixel clock, Vsync, Hsync, DE, and pixel data for video mode
- Supports AXI interface for transmission and reception of packets
- Supports APB interface for register access
MIPI DSI-2 Transmitter IP Core Block Diagram
説明
Renesas' MIPI® DSI℠-2 Transmitter IP is compliant with the Specification for Display Serial Interface 2 (DSI-2). This IP can be implemented in a DSI-2 host processor and act as a transmitter for image data.
パラメータ
| 属性 | 値 |
|---|---|
| Protocol | MIPI |
| Function | Controller, Transmitter |
| Process | Soft macro |
| Data Rate (Mbps) | 80 to 4500 |
| Interface | PPI, AMBA® APB, AXI, Video |
