Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | |
| Pkg. Code: | |
| Lead Count (#): | |
| Pkg. Dimensions (mm): | |
| Pitch (mm): |
Environmental & Export Classifications
| Pb (Lead) Free | |
| Moisture Sensitivity Level (MSL) | |
| ECCN (US) | |
| HTS (US) |
Product Attributes
| Protocol | PCIe 2.1, USB 3.0 |
| Function | PHY |
| Process | TSMC 28nm HPC+ |
| Interface | PIPE |
| Number of Channels | 1, 2, 4, 8 lanes |
| Supply Voltage Range (V) | Core: 0.90 or 1.0V, I/O: 1.8V |
| Data Rate RS-485/RS-232 | - |
Resources for SANDYMLS+
Description
Renesas' SerDes PHY IP, a useful analog transceiver hard macro for various high-speed serial interfaces, is fabricated using TSMC's 28nm HPC+ (High-Performance Compact Plus) process technology. This macro is designed for PCI Express® 2.1 and USB 3.0 SuperSpeed®.
*1: There are some restrictions on the use cases of PCI Express 2.1 and USB 3.0 SuperSpeed. Please contact us for detailed information before purchasing the product.
