特長
- Integrated Ethernet communication controller (Ethernet MAC) according to the IEEE 802.3 standard
- The controller supports these operation modes
- 10/100/1000Mbps
- Full-duplex operation
- PHY interface: MII, RMII, GMII, RGMII, and SGMII (SGMII is Standard v1.8 and using an external converter)
- Supports receive filtering (for L2 ~ L4)
- Supports Jumbo Frame (up to 16KB)
- Supports IEEE 802.1AS-rev
- Supports IEEE 802.1Qci Ingress Policing
- Supports IEEE 802.1Qav Credit-Based Shaper (CBS)
- Supports IEEE 802.1Qbv Time Aware Shaper (TAS)
- Supports IEEE 802.3br Interspersed Express Traffic (IET)
- Supports IEEE 802.1Qbu Frame Preemption
- Automatic Tx/Rx Cyclic Redundancy Check (CRC) computed by the Ethernet controller
- Interrupt-free data transfer between system memory and network
- Integrated Direct Memory Access (DMA) for data transfers from/to system memory
- Integrated First In, First Out (FIFO) in the Ethernet controller
- Test modes internal loopback
Ethernet Time-Sensitive Networking End Station IP Block Diagram
説明
Renesas' Ethernet Time-Sensitive Networking (TSN) End Station IP provides interface features for end stations in Ethernet time-sensitive networking. This IP includes an Ethernet controller that conforms to the IEEE 802.3 standard and standards related to Ethernet TSN. The IP has a standard, easy-to-use interface that is easy to implement.
パラメータ
| 属性 | 値 |
|---|---|
| Protocol | Ethernet TSN |
| Function | End Station |
| Process | Soft macro |
| Data Rate (Mbps) | 10, 100, 1000 |
| Interface | AMBA® APB, AXI |
