特長
- Can be used for an analog receiver for the following interfaces:
- MIPI Alliance Specification for D-PHY Version 2.1 15 December 2016
- MIPI Alliance Specification for CSI-2 (Camera Serial Interface 2)
- Technology is TSMC's 22nm ULP (Ultra-Low Power)
- Supply voltage can be applied - 0.9V for core voltage, 1.8V for I/O voltage
- Maximum data rate of each channel is 1.5Gbps in High-Speed mode
MIPI D-PHY Receiver for CSI-2 IP (TSMC 22nm ULP) Block Diagram
説明
Renesas' MIPI® D-PHY™ Receiver IP is a 4 or 2 data lanes receiver hard macro for CSI-2® fabricated using TSMC's 22nm ULP (Ultra-Low Power) process.
パラメータ
| 属性 | 値 |
|---|---|
| Protocol | MIPI |
| Function | D-PHY, Receiver |
| Process | Soft macro & TSMC 22nm ULP |
| Data Rate (Mbps) | 1500 |
| Interface | CSI-2, PPI |
| Number of Channels | 4 |
| Supply Voltage Range (V) | Core: 0.9V, I/O: 1.8V |
