特長
- FPD-Link Receiver can be used for an analog receiver with the ANSI/TIA/EIA-644 interface (Except for the voltage range of VIN)
- Technology is TSMC 22nm (Ultra-Low Power) 1p10M
- Supply voltage can be applied at 0.9V for the voltage, 1.8V for the I/O voltage
- With an input clock at 85MHz, the maximum data rate of each channel is 595Mbps
- Clock Monitor function can detect an anomaly status of the input clock (CLK_P/N) and the Phase-Locked Loop (PLL) output clock
Flat Panel Display Link Receiver IP (TSMC 22nm ULP) Block Diagram
説明
Renesas' Flat Panel Display Link (FPD-Link) Receiver is a useful 5-channel LVDS receiver. This IP enables the 1:7 serial-to-parallel converting of TSMC's 22nm ULP (Ultra-Low Power) process.
パラメータ
| 属性 | 値 |
|---|---|
| Protocol | FPD-Link |
| Function | Receiver |
| Process | TSMC 22nm ULP |
| Data Rate (Mbps) | 595 |
| Interface | LVDS |
| Number of Channels | 5 |
| Input Freq (MHz) | 85 - 85 |
| Supply Voltage Range (V) | Core: 0.9V, I/O: 1.8V |
