特長
- True Dual-Ported memory cells which allow simultaneous reads of the same memory location
- 7005 easily expands data bus width to 16 bits or more
- Interrupt Flag
- On-chip port arbitration logic
- Full on-chip hardware support of semaphore signaling between ports
- Fully asynchronous operation from either port
- Battery backup operation—2V data retention
- TTL-compatible, single 5V (±10%) power supply
- Available in 68-pin PGA, PLCC, and 64-pin TQFP packages
- Industrial temperature range (-40C to +85C) is available
7005 - Block Diagram
説明
The 7005 is a high-speed 8K x 8 Dual-Port Static RAM designed to be used as a stand-alone 64K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. An automatic power down feature controlled by CE permits the on-chip circuitry of each port to enter a very low standby power mode. Military grade product in compliance with MIL-PRF-38535 QML is available.
パラメータ
| 属性 | 値 |
|---|---|
| Core Voltage (V) | 5 |
| Bus Width (bits) | 8 |
| Density (Kb) | 64 |
| Pkg. Code | GU68, PLG68, PNG64 |
| Interface | Async |
| I/O Type | 5.0 V TTL |
| Access Time (ns) | 15, 20, 35 |
| Temp. Range (°C) | -40 to 85°C, 0 to 70°C |
| Architecture | Dual-Port |
| Organization | 8K x 8 |
| Function | Busy, Interrupt, Master, Semaphore, Slave |
ナレッジベース
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エラーメッセージ"renesas-cpg-mssr e6150000.clock-controller: Cannot get module clock 617: -2"がカーネルログで表示される。
... domain a3vc: -2 [ 83.685774] uvcs: probe of fe8df000.vcp4 failed with error -2 [ 83.693509] uvcs fe900000.vcp4: deferred probe timeout, ignoring dependency [ 83.700587] uvcs: probe of fe900000.vcp4 failed with error -110 Yocto 5.1.0では、M3 v3 SK(RTP8J77961ASKB0SK0SA05A) は動画を再 ...
2021年8月31日
