Features
- Conversion method: Successive approximation
- Resolution: 12/10/8-bit selectable
- Conversion time: 0.4μs
- Differential nonlinearity (DNL): -1LSB(Min.)/+1LSB(Max.)
- Integral nonlinearity (INL): -2LSB(Min.)/+2LSB(Max.)
- Supply voltage: VCCA = 2.7V to 3.6V
- Analog input range: 0 to VREF, single-ended, no multiplexer included
- Process: TSMC CLN40LP
12-bit, 2.5Msps, 3V, 0.4µs, SAR Analog-to-Digital Converter IP Block Diagram
Description
The AT40LADC000112206BSAA1 is a 12-bit, 2.5Msps, 3V, 0.4µs, successive approximation register (SAR) analog-to-digital converter (A/D) that is fabricated using TSMC's CLN40LP (CMOS Logic Node 40nm Low Power (LP)) process technology.
Parameters
| Attributes | Value |
|---|---|
| Product Category | ADC |
| Method | Successive Approximation Register |
| Process | TSMC CLN40LP |
| Analog Supply Voltage (V) | 2.7 - 3.6 |
| Digital Supply Voltage (V) | 1.04 - 1.26 |
| Temp. Range (°C) | -40°C to 125°C |
| Number of Channels | 1 |
| Conversion Rate (Max) (kSPS) | 2500 |
| No-Load Operating Current | 0.7mA (Typ.), 1.1mA (Max.) |
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