Features
- Universally compatible pinout and command set
- Standard block architecture
- Supports quad I/O, QPI, and XiP operations
- Double transfer rate (DTR) operation up to 84MHz
- SPI clock frequency up to 133MHz
- Continuous read, wrap, and burst modes for XiP
AT25xxx NOR Flash Block Diagram
Description
The AT25QF0641C is a 64Mbit serial peripheral interface (SPI) flash memory device designed for use in a wide variety of high-volume industrial, consumer, and connectivity applications. It stores program code that can be copied from flash memory to embedded or external RAM during system boot. It also supports direct code execution from flash memory through execute-in-place (XiP) operation.
Parameters
| Attributes | Value |
|---|---|
| Memory Class | Standard Flash |
| Memory Density | 64 |
| Operating Voltage Range (V) | 2.7 - 3.6 |
| Speed | 133 MHz |
| Interface | Quad SPI, QPI |
| Temp. Range (°C) | -40 to +85°C |
| Deep Power Down (µA) | 0.7 |
| Read Current (mA) | 5 |
| Key Benefit | Standard features |
Product Comparison
 | | |
| AT25QF0641C | AT25SF0641C | |
| Operating Voltage Range | 2.7 - 3.6 | 2.7 - 3.6 |
| Interface | QPI, Quad SPI | Dual SPI, QPI, Quad SPI, Single SPI |
| Read Current (mA) | 5 | 5 |
Application Block Diagrams
 | Scalable Medium-Graphics HMI Platform Scalable medium-graphics HMI design combines display, touch, and voice interaction across integrated and connected architecture variants. |
| Part Number | Status | Samples | Longevity | Stock | Package | Budgetary Price (USD) | Carrier Type | Moisture Sensitivity Level (MSL) | Assembly Location |
|---|---|---|---|---|---|---|---|---|---|
| AT25QF0641C-MUB-T | Active | Available | 2036 Aug | Out of Stock | 5x6 DFN | 1ku | $0.923 | Tape & Reel | 3 | CHINA |
| AT25QF0641C-SUB-T | Active | Available | 2036 Aug | Out of Stock | SOICW | 1ku | $0.832 | Tape & Reel | 3 | CHINA |
| AT25QF0641C-MBUB-T | Preview | N/A | 2036 Aug | Out of Stock | 3x4 DFN | 1ku | $0.923 | Tape & Reel | 3 | CHINA |
| AT25QF0641C-MCUB-T | Preview | N/A | 2036 Aug | Out of Stock | 4x4 DFN | 1ku | $0.935 | Tape & Reel | 3 | CHINA |
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- DatasheetPDF 4.15 MB R10DS0425EU0100 Rev.1.00 Aug 07, 2026The AT25SF0641C/AT25QF0641C is a 64Mbit SPI Serial NOR Flash memory operating from 2.7V to 3.6V. This datasheet describes its features, functions, command set, performance characteristics, package pinout, package specifications, and ordering information to support application design.
- Application NotePDF 884 KB R10AN0038EU0100 Rev.1.00 Mar 10, 2026This application note discusses endurance and data retention in NOR Flash memory products. It describes the structure and operation of the NOR Flash transistor, the mechanisms of NOR Flash device failure and oxide degradation which limit endurance and data retention. It explains JEDEC-based test procedures for certifying endurance and data retention specifications and ways to mitigate limitations. The first part of this document and the appendix provide background for understanding the issue. The later sections describe practical scenarios of interest to most customers.
- Application NotePDF 695 KB AN503 Sep 05, 2025Explores thermal resistance in integrated circuits (ICs) and details its role in managing heat from power consumption to ensure reliable operation. Proper thermal management enhances IC performance and longevity. Thermal resistance, measured in °C/W, quantifies heat flow resistance from the silicon die to the environment or PCB, with key types including junction-to-case (θJC), case-to-ambient (θCA), junction-to-ambient (θJA), and junction-to-board (θJB).
- Application NotePDF 2.62 MB AN500 Feb 13, 2024AI-generated Summary: NOR Flash memory requires an erase operation before programming, which occurs in three phases: Pre-Program, Erase, and Recovery. The erase process affects entire blocks simultaneously, not byte-by-byte. Memory cells use floating gate MOSFETs to store data, organized into arrays of rows (Word-Lines) and columns (Bit-Lines). Physical Blocks contain multiple Logical Blocks and share common p-wells and Bit-Lines, impacting operation. Smaller Logical Blocks enable improved erase performance through parallelization. Understanding these processes and potential interruptions is crucial for designing reliable systems.
- Application NotePDF 710 KB AN502 Jan 24, 2024AI-generated Summary: Renesas NOR flash devices require decoupling capacitors close to VCC and GND pins to stabilize voltage, typically 1 μF with an optional 100 nF capacitor. Pull-up resistors are recommended on CS#, WP#/IO2, and HOLD#/IO3 pins to ensure proper signal states and facilitate debugging. Signal routing should minimize trace length and maintain a solid ground plane for high-speed signals. Power supply must rise monotonically during power-up. Basic system bring-up involves verifying installation, voltage levels, and SPI communication using manufacturer/device ID commands. Software drivers depend on host MCU architecture; Renesas offers example drivers and support. Correct erase/program sequences include write-enable, erase/program commands, and status checks. Tools for programming include flash loader plug-ins and debug probes. Switching from single to quad-SPI involves setting the quad-enable bit, changing pin functions. Dummy cycles introduce necessary wait times during read commands to accommodate latency.
- GuidePDF 790 KB PBFLASH03102022 Jun 16, 2023
- DocumentPDF 1 MB R10DS0315EU0000 Rev.0.00 Jun 28, 2022
- Application NotePDF 794 KB May 12, 2022AI-generated Summary: Renesas NOR flash devices implement multiple protection methods to safeguard memory arrays, status registers, flash states, and resets from accidental or intentional modifications. Protection types include hardware-based write protection via the WP pin and software-based protection through commands controlling status registers and memory blocks. Memory array protection schemes include individual block protection, allowing sector-level lock/unlock, and memory edge protection, which protects contiguous regions aligned to memory edges. Status register protection indirectly secures memory by blocking changes to protection states. Detailed command sets and register bits configure these protections, ensuring robust flash memory integrity.
- Application NotePDF 663 KB Oct 18, 2021AI-generated Summary: Proper power-up and power-down sequencing is critical for NOR Flash memory operation to ensure reliable system performance. The power supply voltage must ramp up monotonically without dips, reaching the minimum operational voltage within specified timing to avoid corrupted initialization. Reset methods, including hardware and JEDEC resets, help ensure the device starts from a known state. Brown-out conditions and power cycling require careful handling to prevent data corruption and ensure stable operation. The document covers power sequencing, reset types, brown-out recovery, power-down, and power-saving modes, providing essential guidelines for system engineers and application developers.
- Application NotePDF 313 KB Jul 17, 2020AI-generated Summary: PCB design for Adesto memory devices requires careful placement of decoupling capacitors close to VCC and GND pins to minimize voltage fluctuations caused by parasitic inductance and capacitance in PCB traces. Proper capacitor selection and placement reduce signal integrity issues, EMI, and noise. Design guidelines vary by package type (SOIC, UDFN, WLCSP, BGA) and PCB layer count. Signal routing rules ensure reliable data and control signals. Special cases include parallel devices, reset signal handling, and test point integration. The document provides detailed layout recommendations for each package type to optimize device performance and reliability.
- Product Change NoticePDF 528 KB Jun 26, 2020
- DatasheetPDF 4.15 MB R10DS0425EU0100 Rev.1.00 Aug 07, 2026The AT25SF0641C/AT25QF0641C is a 64Mbit SPI Serial NOR Flash memory operating from 2.7V to 3.6V. This datasheet describes its features, functions, command set, performance characteristics, package pinout, package specifications, and ordering information to support application design.
Recommended Documents (1)
- DatasheetPDF 4.15 MB R10DS0425EU0100 Rev.1.00 Aug 07, 2026The AT25SF0641C/AT25QF0641C is a 64Mbit SPI Serial NOR Flash memory operating from 2.7V to 3.6V. This datasheet describes its features, functions, command set, performance characteristics, package pinout, package specifications, and ordering information to support application design.
Datasheets (1)
- GuidePDF 790 KB PBFLASH03102022 Jun 16, 2023
Manuals & Guides (1)
- Application NotePDF 884 KB R10AN0038EU0100 Rev.1.00 Mar 10, 2026This application note discusses endurance and data retention in NOR Flash memory products. It describes the structure and operation of the NOR Flash transistor, the mechanisms of NOR Flash device failure and oxide degradation which limit endurance and data retention. It explains JEDEC-based test procedures for certifying endurance and data retention specifications and ways to mitigate limitations. The first part of this document and the appendix provide background for understanding the issue. The later sections describe practical scenarios of interest to most customers.
- Application NotePDF 695 KB AN503 Sep 05, 2025Explores thermal resistance in integrated circuits (ICs) and details its role in managing heat from power consumption to ensure reliable operation. Proper thermal management enhances IC performance and longevity. Thermal resistance, measured in °C/W, quantifies heat flow resistance from the silicon die to the environment or PCB, with key types including junction-to-case (θJC), case-to-ambient (θCA), junction-to-ambient (θJA), and junction-to-board (θJB).
- Application NotePDF 2.62 MB AN500 Feb 13, 2024AI-generated Summary: NOR Flash memory requires an erase operation before programming, which occurs in three phases: Pre-Program, Erase, and Recovery. The erase process affects entire blocks simultaneously, not byte-by-byte. Memory cells use floating gate MOSFETs to store data, organized into arrays of rows (Word-Lines) and columns (Bit-Lines). Physical Blocks contain multiple Logical Blocks and share common p-wells and Bit-Lines, impacting operation. Smaller Logical Blocks enable improved erase performance through parallelization. Understanding these processes and potential interruptions is crucial for designing reliable systems.
- Application NotePDF 710 KB AN502 Jan 24, 2024AI-generated Summary: Renesas NOR flash devices require decoupling capacitors close to VCC and GND pins to stabilize voltage, typically 1 μF with an optional 100 nF capacitor. Pull-up resistors are recommended on CS#, WP#/IO2, and HOLD#/IO3 pins to ensure proper signal states and facilitate debugging. Signal routing should minimize trace length and maintain a solid ground plane for high-speed signals. Power supply must rise monotonically during power-up. Basic system bring-up involves verifying installation, voltage levels, and SPI communication using manufacturer/device ID commands. Software drivers depend on host MCU architecture; Renesas offers example drivers and support. Correct erase/program sequences include write-enable, erase/program commands, and status checks. Tools for programming include flash loader plug-ins and debug probes. Switching from single to quad-SPI involves setting the quad-enable bit, changing pin functions. Dummy cycles introduce necessary wait times during read commands to accommodate latency.
Application Notes & White Papers (8)
- Product Change NoticePDF 528 KB Jun 26, 2020
Product Notices (PCN, EOL, etc) (2)
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- Development ToolµISP is a compact standalone and universal solution, specifically designed for production environments, based on Algocrafts WriteNow! Technology. This is a standard tool for many families and devices and supports multi programming protocol (JTAG, SPI, UART, DAP, SWD, I2C, BDM, custom protocol, etc).Provided By: Algocraft Srl
- Development ToolWriteNow! Series of In-System Programmers is a breakthrough in the programming industry. The programmers support a large number of devices (microcontrollers, memories, CPLDs and other programmable devices) from various manufacturers and have a compact size for easy ATE/fixture integration. They work in standalone or connected to a host PC (RS-232, LAN and USB connections are built-in), and are provided with easy-to-use software utilities.Provided By: Algocraft Srl
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- Development ToolµISP is a compact standalone and universal solution, specifically designed for production environments, based on Algocrafts WriteNow! Technology. This is a standard tool for many families and devices and supports multi programming protocol (JTAG, SPI, UART, DAP, SWD, I2C, BDM, custom protocol, etc).Provided By: Algocraft Srl
- Development ToolWriteNow! Series of In-System Programmers is a breakthrough in the programming industry. The programmers support a large number of devices (microcontrollers, memories, CPLDs and other programmable devices) from various manufacturers and have a compact size for easy ATE/fixture integration. They work in standalone or connected to a host PC (RS-232, LAN and USB connections are built-in), and are provided with easy-to-use software utilities.Provided By: Algocraft Srl
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