Features
- Includes a loop filter
- VCO operating range: 580MHz to 1250MHz
- Output frequency range: 72.5MHz to 1250MHz
- Input frequency range: 9.6MHz to 100MHz
- Multiplying (output frequency/phase frequency detector (PFD) frequency)
- 40 to 120
- Divider
- 7-bit feedback divider (N divider)
- 3-bit input divider (M divider)
- Selectable feedback loop for skew adjust
- Power-down mode is supported
- Multiple outputs with post-divider
- SSC input is available (recommend triangle profile)
- Power-on sequence is constraint-free
- Standby (STBY) sequence is constraint-free
- Process: TSMC 40nm LP
Analog PLL IP for Frequency Multiplying Block Diagram
Description
The ABFPPLR17V19B0B is a 1.25GHz analog phase-locked loop (PLL) IP for frequency multiplying using TSMC's 40nm Low Power (LP) process technology.
Parameters
| Attributes | Value |
|---|---|
| Product Category | PLL |
| Process | TSMC 40nm LP |
| VCO Operating Range (MHz) | 580 - 1250 |
| Input Freq (MHz) | 9.6 - 100 |
| Output Freq Range (MHz) | 72.5 - 1250 |
| Analog Supply Voltage (V) | 1.04 - 1.26 |
| Digital Supply Voltage (V) | 1.04 - 1.26 |
| Spread Spectrum | No |
| Temp. Range (°C) | -40°C to +125°C |
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