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9DB108

Obsolete

8-Output Differential Buffer for PCIe Gen 1

NOTICE - The following device(s) are recommended alternatives:
9DBL0841 - 8-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer
9DBL0851 - 8-Output 3.3V PCIe Zero-Delay/Fanout Clock Buffer
9DB803 - 8-output Differential Buffer for PCIe Gen2

Overview

The 9DB108 8-output differential buffer for PCIe Gen 1 is not recommended for new designs. The 9DB803 8-output differential buffer for PCIe Gen 2 is the recommended replacement.

  • Supports tight ppm accuracy clocks for Serial-ATA
  • Spread spectrum modulation tolerant, 0% to -0.5% down spread and ± 0.25% center spread
  • Supports undriven differential output pair in PD# and SRC_STOP# for power management

Documentation

Design & Development

ECAD Models

Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.

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Videos & Training

PCIe Clocking Architectures (Common and Separate)

This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.

Watch the Video Series Below

Video List
PCIe Clocking Architectures (Common and Separate)
PCIe Common Clock Architecture and its Impact on Clocking
PCIe Separate Reference without Spread Clock Architecture
PCIe Separate Reference Clock With Independent Spread (SRIS) Architecture Overview