無線シンクロナイザ＆JESD204B/Cクロックジッタ減衰器

ページセクションへ移動：

ルネサスの無線クロックシンクロナイザおよびJESD204B/Cクロックジッタ減衰器は、eCPRIやCPRIを用いた高密度・多チャンネルRF設計において、最高の4G/5G 無線EVM性能を実現する優れた近端位相ノイズおよび、業界トップクラスの位相ノイズ性能を提供します。

シングルチップの無線クロックシンクロナイザデバイスは高性能RF PLLを備えたデジタルPLL（DPLL）を統合し、PTP（Precision Timing Protocol、IEEE 1588）、同期イーサネット、1PPS入出力、高精度のクロック位相アライメントに対応します。

これらのデバイスは入力基準クロックから実質的にすべての位相ノイズを除去し、データコンバータの基準クロックの生成と同期に適しています。

セレクションテーブル

Processing table

	Outputs (#)	Inputs (#)	Input Freq (MHz)	DPLL Channels (#)	JESD204B/C Compliant	Output Freq Range (MHz)	Frequency Plan	Output Skew (ps)	Adjustable Phase	Noise Floor (dBc/Hz)	Phase Noise Supports GSM	Output Type	Synthesis Mode	Input Ref. Divider Resolution (bits)	Feedback Divider Resolution (bits)	Output Divider Resolution (bits)	Supply Voltage (V)	Input Redundancy	Advanced Features	Pkg. Type	Lead Count (#)
(16) 注目の製品 (0) その他製品	10 11 12 15 16 18 24	2 4 10	最大値 Input frequency (in MHz). 最小値 Input frequency (in MHz).	最大値 Device features a digital phase-locked loop (DPLL). 最小値 Device features a digital phase-locked loop (DPLL).	No Yes	最大値 Output frequency range (in MHz). 最小値 Output frequency range (in MHz).	1966.08 / Output_Divider 2400 / Output_Divider 2457.6 / Output_Divider 2500 / Output_Divider 2949.12 / Output_Divider 3670-3868 / Output_Divider 3686.4 / Output_Divider 3932.16 / Output_Divider	0 28 37 41 50 70 74 100	Yes	-165 -161 -160.2 -160 -158.7 -158	No Yes	HSTL LVCMOS LVDS LVHSTL LVPECL LVTTL	Fractional Integer	3 4 12 15	12 15 32 48	7 8 32	最大値 Power supply voltage or voltage range of the device. 最小値 Power supply voltage or voltage range of the device.	Auto-switch Digital holdover Hitless switch Holdover Input Monitor Input Switching JESD204B Manual input switch Manual switch Phase Delay Phase-slope limiting Programmable Clock Revertive and non-revertive switch	1PPS DCO Holdover IEEE 1588 Input Switching JESD204B JESD204C PWM Encoder/Decoder Phase Delay Programmable Clock T-BC T-TSC Class C ToD eEEC	CABGA VFQFPN	72 76 81 88 100
型名	Logical Operator	Logical Operator			Logical Operator		Logical Operator	Logical Operator	Logical Operator	Logical Operator	Logical Operator	Logical Operator	Logical Operator	Logical Operator	Logical Operator	Logical Operator		Logical Operator	Logical Operator	Logical Operator	Logical Operator
8V19N850 PDF 無線シンクロナイザ	16	2	0.000001 - 1000	2	Yes	0.000001 - 1000	2500 / Output_Divider, 2949.12 / Output_Divider, 3670-3868 / Output_Divider	74	Yes	-165	Yes	LVCMOS, LVDS, LVPECL	Fractional, Integer	3	32	7	3.3, 2.5, 1.8	Digital holdover, Hitless switch, Input Monitor, Phase-slope limiting	1PPS, DCO, IEEE 1588, JESD204B, JESD204C, T-BC, T-TSC Class C, eEEC	VFQFPN	88
8V19N882 PDF JESD204B/C クロックジッタ減衰器	16	2	0.00375 - 2000	0	Yes	0.192 - 6000	3932.16 / Output_Divider	100	Yes	-160	Yes	LVDS, LVPECL	Integer	15	15	7	3.3, 2.5, 1.8	Auto-switch, Holdover, Input Monitor, Manual input switch	Holdover, Input Switching, JESD204B	VFQFPN	76
8V19N470 PDF Clock Jitter Attenuator	10	2	0.008 - 307.2	0	No	15.36 - 2949.12	2457.6 / Output_Divider, 2500 / Output_Divider, 2949.12 / Output_Divider	41	Yes	-161	Yes	LVDS, LVPECL	Integer	15	15	8	3.3	Auto-switch, Holdover, Input Monitor, Manual switch and more...	Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock	CABGA	81
8V19N472 PDF Clock Jitter Attenuator	11	2	0.008 - 307.2	0	No	15.36 - 2949.12	2457.6 / Output_Divider, 2500 / Output_Divider, 2949.12 / Output_Divider	28	Yes	-158.7	Yes	LVDS, LVPECL	Integer	15	15	8	3.3	Auto-switch, Holdover, Input Monitor, Manual switch and more...	Holdover, Input Switching, Phase Delay, Programmable Clock	CABGA	81
8V19N474 PDF JESD204B/C Clock Jitter Attenuator	12	2	0.008 - 250	0	No	15.625 - 2500	2400 / Output_Divider, 2500 / Output_Divider	70	Yes	-161	Yes	LVDS, LVPECL	Fractional, Integer	15	15	8	3.3	Auto-switch, Input Monitor, Manual switch	Holdover, Input Switching, Phase Delay	CABGA	81
8V19N480 PDF JESD204B/C Clock Jitter Attenuator	18	4	30.72 - 500	0	Yes	20.48 - 1474.56	2949.12 / Output_Divider	37	Yes	-161	Yes	LVDS, LVPECL	Integer	12	12	8	3.3	Auto-switch, Holdover, Input Monitor, Manual switch and more...	Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock	CABGA	100
8V19N490 PDF JESD204B/C Clock Jitter Attenuator	18	4	1.92 - 2000	0	Yes	18.432 - 2949.12	2949.12 / Output_Divider	100	Yes	-160	Yes	LVDS, LVPECL	Integer	12	12	8	3.3	Auto-switch, Holdover, Input Monitor, Manual switch and more...	Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock	CABGA	100
8V19N490-19 PDF JESD204B/C Clock Jitter Attenuator	18	4	1.92 - 2000	0	Yes	12.288 - 1966.08	1966.08 / Output_Divider	100	Yes	-160	Yes	LVDS, LVPECL	Integer	12	12	8	3.3	Auto-switch, Holdover, Input Monitor, Manual switch and more...	Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock	CABGA	100
8V19N490-24 PDF JESD204B/C Clock Jitter Attenuator	18	4	1.92 - 2000	0	Yes	15.36 - 2457.6	2457.6 / Output_Divider	100	Yes	-160	Yes	LVDS, LVPECL	Integer	12	12	8	3.3	Auto-switch, Holdover, Input Monitor, Manual switch and more...	Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock	CABGA	100
8V19N490A JESD204B/C Clock Jitter Attenuator	18	4	1.92 - 2000	0	Yes	18.432 - 2949.12	2949.12 / Output_Divider	100	Yes	-160	Yes	LVDS, LVPECL	Integer	12	12	8	3.3	Auto-switch, Holdover, Input Monitor, Manual switch and more...	Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock	CABGA	100
8V19N490B PDF JESD204B/C Clock Jitter Attenuator	18	4	1.92 - 2000	0	Yes	18.432 - 2949.12	2949.12 / Output_Divider	100	Yes	-160	Yes	LVDS, LVPECL	Integer	12	12	8	3.3	Auto-switch, Holdover, Input Monitor, Manual switch and more...	Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock	CABGA	100
8V19N491-24 PDF JESD204B/C Clock Jitter Attenuator	15	2	1.92 - 2000	0	Yes	12.288 - 2457.6	2457.6 / Output_Divider	100	Yes	-160	Yes	LVDS, LVPECL	Integer	12	12	8	3.3	Auto-switch, Holdover, Input Monitor, Manual switch and more...	Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock	VFQFPN	88
8V19N491-36 PDF JESD204B/C Clock Jitter Attenuator	18	4	30.72 - 2000	0	Yes	18.432 - 3686.4	3686.4 / Output_Divider	100	Yes	-160	Yes	LVDS, LVPECL	Integer	12	12	8	3.3	Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock	Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock	CABGA	100
8V19N492 PDF JESD204B/C クロックジッタ減衰器	15	2	1.92 - 2000	0	Yes	18.432 - 2949.12	2949.12 / Output_Divider	0	Yes	-160	Yes	LVDS, LVPECL	Integer	12	12	8	3.3	Auto-switch, Holdover, Input Monitor, Manual switch and more...	Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock	VFQFPN	88
8V19N492-39 PDF JESD204B/C Clock Jitter Attenuator	15	2	30.72 - 2000	0	Yes	19.6608 - 3932.16	3932.16 / Output_Divider	100	Yes	-160.2	Yes	LVDS, LVPECL	Integer	12	12	8	3.3	Auto-switch, Holdover, Input Monitor, Manual switch and more...	Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock	VFQFPN	88
RC38612 PDF 無線アクセスネットワーク機器用シンクロナイザ - 6チャネル	24	10	0.001 - 1000	6	Yes	0.0000005 - 1000		50	Yes	-158	No	HSTL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL	Fractional, Integer	4	48	32	3.3, 2.5, 1.8	Digital holdover, Hitless switch, Input Monitor, Phase-slope limiting	1PPS, DCO, IEEE 1588, JESD204B, JESD204C, PWM Encoder/Decoder and more...	VFQFPN	72

Tips for Using This Parametric Table:

Hide Filters button in header: Collapse or expands filters
Column sort buttons in header: Sort Column alphabetically / numerically descending or ascending
Reset button in header: Reset all filters to the page default
Full Screen button in header: Expand the table to full screen view (user must close out of full screen before they can interact with rest of page)
Export button in header: Export the filtered results of the table to an Excel document
Filter parts search bar in header: Type to filter table results by part number
Hide column button in column headers: Select to hide columns in table
AND / OR toggle switches in header: Toggles the logic of this particular filter to be “AND” or “OR” logic for filtering results
Multiselect checkboxes at beginning of each row in table: Select these checkboxes to compare products against each other
Document icon next to product name in row: View the featured document for this product
Chip icon next to the right of the document icon in row: View the block diagram for this product
Cart icon to the right of the chip icon: Indicates that samples are available for this product

ドキュメント


分類	タイトル	日付
概要	RF Timing Family Product Overview PDF 331 KB	2021年3月11日
1 item

ビデオ&トレーニング

8V19N880, 8V19N882 Low-Power 4G & 5G RF Clock Jitter Attenuators

The 8V19N880 and 8V19N882 JESD204B/C clock jitter attenuators deliver low phase noise and exceptional jitter performance as low as 74fs RMS and -90dB spurious attenuation for mission-critical industrial data converter applications in wireless radio, test and measurement, instrumentation, and high-performance imaging. They support frequencies up to 3932.16MHz (up to 6GHz with an external VCO) and feature 16 and 18 integrated differential outputs to deliver a first-in-class balance of high performance, low voltage and low power consumption with 1.8V support.

Video List

8V19N880, 8V19N882 Low-Power 4G & 5G RF Clock Jitter Attenuators

8V19N850 5G Radio Synchronizer