
ルネサスの無線クロックシンクロナイザおよびJESD204B/Cクロックジッタ減衰器は、eCPRIやCPRIを用いた高密度・多チャンネルRF設計において、最高の4G/5G 無線EVM性能を実現する優れた近端位相ノイズおよび、業界トップクラスの位相ノイズ性能を提供します。
シングルチップの無線クロックシンクロナイザデバイスは高性能RF PLLを備えたデジタルPLL(DPLL)を統合し、PTP(Precision Timing Protocol、IEEE 1588)、同期イーサネット、1PPS入出力、高精度のクロック位相アライメントに対応します。
これらのデバイスは入力基準クロックから実質的にすべての位相ノイズを除去し、データコンバータの基準クロックの生成と同期に適しています。
Outputs (#) |
Inputs (#) |
Input Freq (MHz) |
DPLL Channels (#) |
JESD204B/C Compliant |
Output Freq Range (MHz) |
Frequency Plan |
Output Skew (ps) |
Adjustable Phase |
Noise Floor (dBc/Hz) |
Phase Noise Supports GSM |
Output Type |
Synthesis Mode |
Input Ref. Divider Resolution (bits) |
Feedback Divider Resolution (bits) |
Output Divider Resolution (bits) |
Supply Voltage (V) |
Input Redundancy |
Advanced Features |
Pkg. Type |
Lead Count (#) |
|
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
型名 | |||||||||||||||||||||
無線シンクロナイザ | 16 | 2 | 0.000001 - 1000 | 2 | Yes | 0.000001 - 1000 | 2500 / Output_Divider, 2949.12 / Output_Divider, 3670-3868 / Output_Divider | 74 | Yes | -165 | Yes | LVCMOS, LVDS, LVPECL | Fractional, Integer | 3 | 32 | 7 | 3.3, 2.5, 1.8 | Digital holdover, Hitless switch, Input Monitor, Phase-slope limiting | 1PPS, DCO, IEEE 1588, JESD204B, JESD204C, T-BC, T-TSC Class C, eEEC | VFQFPN | 88 |
JESD204B/C クロックジッタ減衰器 | 16 | 2 | 0.00375 - 2000 | 0 | Yes | 0.192 - 6000 | 3932.16 / Output_Divider | 100 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 15 | 15 | 7 | 3.3, 2.5, 1.8 | Auto-switch, Holdover, Input Monitor, Manual input switch | Holdover, Input Switching, JESD204B | VFQFPN | 76 |
Clock Jitter Attenuator | 10 | 2 | 0.008 - 307.2 | 0 | No | 15.36 - 2949.12 | 2457.6 / Output_Divider, 2500 / Output_Divider, 2949.12 / Output_Divider | 41 | Yes | -161 | Yes | LVDS, LVPECL | Integer | 15 | 15 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | CABGA | 81 |
Clock Jitter Attenuator | 11 | 2 | 0.008 - 307.2 | 0 | No | 15.36 - 2949.12 | 2457.6 / Output_Divider, 2500 / Output_Divider, 2949.12 / Output_Divider | 28 | Yes | -158.7 | Yes | LVDS, LVPECL | Integer | 15 | 15 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, Phase Delay, Programmable Clock | CABGA | 81 |
JESD204B/C Clock Jitter Attenuator | 12 | 2 | 0.008 - 250 | 0 | No | 15.625 - 2500 | 2400 / Output_Divider, 2500 / Output_Divider | 70 | Yes | -161 | Yes | LVDS, LVPECL | Fractional, Integer | 15 | 15 | 8 | 3.3 | Auto-switch, Input Monitor, Manual switch | Holdover, Input Switching, Phase Delay | CABGA | 81 |
JESD204B/C Clock Jitter Attenuator | 18 | 4 | 30.72 - 500 | 0 | Yes | 20.48 - 1474.56 | 2949.12 / Output_Divider | 37 | Yes | -161 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | CABGA | 100 |
JESD204B/C Clock Jitter Attenuator | 18 | 4 | 1.92 - 2000 | 0 | Yes | 18.432 - 2949.12 | 2949.12 / Output_Divider | 100 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | CABGA | 100 |
JESD204B/C Clock Jitter Attenuator | 18 | 4 | 1.92 - 2000 | 0 | Yes | 12.288 - 1966.08 | 1966.08 / Output_Divider | 100 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | CABGA | 100 |
JESD204B/C Clock Jitter Attenuator | 18 | 4 | 1.92 - 2000 | 0 | Yes | 15.36 - 2457.6 | 2457.6 / Output_Divider | 100 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | CABGA | 100 |
JESD204B/C Clock Jitter Attenuator | 18 | 4 | 1.92 - 2000 | 0 | Yes | 18.432 - 2949.12 | 2949.12 / Output_Divider | 100 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | CABGA | 100 |
JESD204B/C Clock Jitter Attenuator | 18 | 4 | 1.92 - 2000 | 0 | Yes | 18.432 - 2949.12 | 2949.12 / Output_Divider | 100 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | CABGA | 100 |
JESD204B/C Clock Jitter Attenuator | 15 | 2 | 1.92 - 2000 | 0 | Yes | 12.288 - 2457.6 | 2457.6 / Output_Divider | 100 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | VFQFPN | 88 |
JESD204B/C Clock Jitter Attenuator | 18 | 4 | 30.72 - 2000 | 0 | Yes | 18.432 - 3686.4 | 3686.4 / Output_Divider | 100 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | CABGA | 100 |
JESD204B/C クロックジッタ減衰器 | 15 | 2 | 1.92 - 2000 | 0 | Yes | 18.432 - 2949.12 | 2949.12 / Output_Divider | 0 | Yes | -160 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | VFQFPN | 88 |
JESD204B/C Clock Jitter Attenuator | 15 | 2 | 30.72 - 2000 | 0 | Yes | 19.6608 - 3932.16 | 3932.16 / Output_Divider | 100 | Yes | -160.2 | Yes | LVDS, LVPECL | Integer | 12 | 12 | 8 | 3.3 | Auto-switch, Holdover, Input Monitor, Manual switch and more... |
Holdover, Input Switching, JESD204B, Phase Delay, Programmable Clock | VFQFPN | 88 |
無線アクセスネットワーク機器用シンクロナイザ - 6チャネル | 24 | 10 | 0.001 - 1000 | 6 | Yes | 0.0000005 - 1000 | 50 | Yes | -158 | No | HSTL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL | Fractional, Integer | 4 | 48 | 32 | 3.3, 2.5, 1.8 | Digital holdover, Hitless switch, Input Monitor, Phase-slope limiting | 1PPS, DCO, IEEE 1588, JESD204B, JESD204C, PWM Encoder/Decoder and more... |
VFQFPN | 72 |
The 8V19N880 and 8V19N882 JESD204B/C clock jitter attenuators deliver low phase noise and exceptional jitter performance as low as 74fs RMS and -90dB spurious attenuation for mission-critical industrial data converter applications in wireless radio, test and measurement, instrumentation, and high-performance imaging. They support frequencies up to 3932.16MHz (up to 6GHz with an external VCO) and feature 16 and 18 integrated differential outputs to deliver a first-in-class balance of high performance, low voltage and low power consumption with 1.8V support.
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Your Guide to Executing pcm4l Software Flawlessly | ブログ | 2021年1月30日 |