特長
- Compliant with Specification for Camera Serial Interface 2 (CSI-2®) Version 3.0
- Compliant with PHY Protocol Interface (PPI) to D-PHY™ Version 2.5
- Compliant with AMBA® APB Protocol Version 2.0
- Supports PPI interface for D-PHY physical layer option
- Supports Renesas original Video Pixel Interface
- Supports APB interface for register access
MIPI CSI-2 Receiver IP Core Block Diagram
説明
Renesas' MIPI® CSI-2® Receiver IP is compliant with the Specification for Camera Serial Interface 2 (CSI-2). This IP can be implemented in a CSI-2 host processor (baseband, application engine) and act as a receiver for image/sensor data.
パラメータ
| 属性 | 値 |
|---|---|
| Protocol | MIPI |
| Function | Controller, Receiver |
| Process | Soft macro |
| Data Rate (Mbps) | 80 to 4500 |
| Interface | CSI-2, DSI, PPI, AMBA® APB, Video |
