特長
- Pinout optimized for DDR5 RDIMM PCB layout
- DDR5 server speeds up to 8800MT/s
- Supports power-down modes to conserve server power
- Supports 1-rank/2-rank DIMM configurations
- Supports SDP, DDP, and 3DS DRAM types
- Provides access to internal control words for configuring device features and adapting to different RDIMM system applications
- I2C and I3C sideband access for asynchronous register access control
- Loopback and pass-through modes
- Package: 8.7 × 14.4mm, 264-FCCSP
RRG5005x Block Diagram
説明
The RRG5005x-B08 is a registering clock driver (RCD) used on DDR5 RDIMMs. Its primary function is to buffer the Command/Address (CA) bus, chip selects, and clock between the host controller and the DRAMs. The RRG5005x-B08 contains two separate channels, which have some common logic such as clocking, but otherwise operate independently of each other. Each channel has a 7-bit double data rate CA bus input, a single parity input, two chip select inputs, and produces two copies of 14-bit single data rate CA bus outputs, and two copies of the chip select outputs. The RCD has a common clock input and PLL, but produces four separate clock pairs to the DRAM channels.
パラメータ
| 属性 | 値 |
|---|---|
| Product Type | Registering Clock Driver |
| Function | DDR5 Gen 5.0 Server RCD |
| Application System | Server |
| Input Voltage Range (V) | 1.06 - 1.16 |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| FCCSP | 8.7 x 14.4 x 0.9 | 264 | 0.6 |
アプリケーション
- RDIMM Modules for Enterprise Servers
- Memory Down Server Motherboards
