ルネサス エレクトロニクス株式会社 (Renesas Electronics Corporation)
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8SLVP1208

アクティブ

2:8 LVPECL Output Fanout Buffer

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特長

  • Eight low-skew, low additive jitter LVPECL output pairs
  • Two selectable, differential clock input pairs
  • Differential pairs can accept the following differential input levels: LVDS, LVPECL, CML
  • Maximum input clock frequency: 2GHz
  • LVCMOS interface levels for the control input (input select)
  • Output skew: 28ps (typical)
  • Propagation delay: 410ps (maximum)
  • Low additive phase jitter, RMS: 54.1fs (maximum) (fREF = 156.25MHz, VPP = 1V, 12kHz to 20MHz)
  • Full 3.3V and 2.5V supply voltage
  • Maximum device current consumption (IEE): 141mA
  • Available in a lead-free (RoHS 6), 28-lead VFQFN package
  • -40 °C to 85 °C ambient operating temperature
クロック分配内の他の製品を探す
8SLVP1208I - Block Diagram
8SLVP1208I - Pinout
8SLVP1208I - Block Diagram
8SLVP1208I - Pinout

説明

The 8SLVP1208 is a high-performance differential LVPECL fanout buffer. The device is designed for the fanout of high-frequency, very-low additive phase-noise clock and data signals. The 8SLVP1208 is characterized to operate from a 3.3V and 2.5V power supply. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVP1208 ideal for those clock distribution applications demanding well-defined performance and repeatability. Two selectable differential inputs and eight low-skew outputs are available. The integrated bias voltage generators enable easy interfacing of single-ended signals to the device inputs. The device is optimized for low power consumption and low additive phase noise.

パラメータ

属性 値
Temp. Range (°C) -40 to 85°C

パッケージオプション

Pkg. Type Pkg. Dimensions (mm) Lead Count (#) Pitch (mm)
VFQFPN 5.0 x 5.0 x 0.8 28 0.5

適用されたフィルター

読込中
読込中

Overview of IDT's 8LSVP (LVPECL) and 8SLVD (LVDS) families of low-jitter fanout buffers from IDT. Fanout buffers are a useful building block of many clock trees, providing signal buffering and multiple low-skew copies of the input signal. IDT's high-performance, low additive phase noise, differential clock fan-out buffers offer up to 2 GHz clock operation, low additive phase jitter (12kHz - 20MHz) of 50 to 100 femtoseconds RMS max, fast output rise & fall times (less than 150ps), and single and dual channel functions (dual: matched propagation delay). Presented by Baljit Chandhoke, Product Marketing Manager at Integrated Device Technology, Inc. To learn more about IDT's industry-leading portfolio of fanout buffers, visit Renesas's RF Buffer page.

 

読込中 読込中