Features
- AMBA® AXI interface
- Conforms to AMBA AXI Protocol v1.0 Specification (ARM IHI 0022B)
- Interface: Master/Slave
- Endian: Little
- Bus Width: 128 bits
- Direct Memory Access Controller (DMAC) functions are provided
- PCIe® specification
- Conforms to PCI Express® Base Specification 5.0
- Supports
- PCIe 1: 2.5GT/s
- PCIe 2: 5.0GT/s
- PCIe 3: 8.0GT/s
- PCIe 4: 16.0GT/s
- PCIe 5: 32GT/s
- Root complex and endpoint applications, Type 0/1 configuration register
- Multiple lane implementations x1
- Lane reversal and polarity inversion
- Maximum data payload size: 4096 bytes
- Maximum read request size: 4096 bytes
- Number of outstanding requests: 1
- PIPE interface
- Supports PIPE 5.2
- Fixed Data-Path: 32-bit
- PCIe 1: 62.5MHz
- PCIe 2: 125MHz
- PCIe 3: 250MHz
- PCIe 4: 500MHz
- PCIe 5: 1MHz
- Message Bus I/F support
- Low Pin Count (LPC) interface support
PCI Express 5.0 Link Controller IP Block Diagram
Description
This IP is a Renesas-developed controller IP for PCI Express® (PCIe®) 5.0. The IP's system interface is based on the AMBA® AXI and PIPE interfaces. It includes a Data Link Layer (DLL). It also has a Transaction Layer for the root complex and endpoint, and Type 0/1 configuration registers. Additionally, the PCI Express 5.0 Link Controller IP has a Direct Memory Access (DMA) controller function and is written in Verilog RTL.
Parameters
| Attributes | Value |
|---|---|
| Protocol | PCIe 5 |
| Function | Controller |
| Process | Soft macro |
| Data Rate (Mbps) | 32GT/s (PCIe 5) |
| Interface | AMBA® AXI, PIPE 5.2 |
| Number of Channels | 1 lane |
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