Package Information
| CAD Model: | View CAD Model |
| Pkg. Type: | |
| Pkg. Code: | |
| Lead Count (#): | |
| Pkg. Dimensions (mm): | |
| Pitch (mm): |
Environmental & Export Classifications
| Pb (Lead) Free | |
| Moisture Sensitivity Level (MSL) | |
| ECCN (US) | |
| HTS (US) |
Product Attributes
| Protocol | PCIe 5 |
| Function | Controller |
| Process | Soft macro |
| Data Rate (Mbps) | 32GT/s (PCIe 5) |
| Interface | AMBA® AXI, PIPE 5.2 |
| Number of Channels | 1 lane |
| Data Rate RS-485/RS-232 | 32GT/s (PCIe 5) |
Resources for IP/PCIE5CTL
Description
This IP is a Renesas-developed controller IP for PCI Express® (PCIe®) 5.0. The IP's system interface is based on the AMBA® AXI and PIPE interfaces. It includes a Data Link Layer (DLL). It also has a Transaction Layer for the root complex and endpoint, and Type 0/1 configuration registers. Additionally, the PCI Express 5.0 Link Controller IP has a Direct Memory Access (DMA) controller function and is written in Verilog RTL.
