Features
- Includes a loop filter
- VCO operating range: 640MHz to 1056MHz
- Output frequency range: 80MHz to 1056MHz
- Input frequency range: 10MHz to 132MHz
- Multiplying (output frequency/phase frequency detector (PFD) frequency)
- 8 to 88
- Divider
- 7-bit feedback divider and 3-bit input divider
- Power-down mode
- Multiple outputs with post-divider
- SSC function available
- Spread type: Down
- Modulation frequency: 20kHz to 33kHz
- Modulation depth: 2.273% to 3.125%
- Process: TSMC 40nm LP
Analog PLL IP with Spread Spectrum Clock Generator Block Diagram
Description
The AT40LPLL0000SG1P1G25V1A is a 1.056GHz analog phase-locked loop (PLL) IP for a spread spectrum clock generator (SSCG) using TSMC's 40nm Low Power (LP) process technology.
Parameters
| Attributes | Value |
|---|---|
| Product Category | PLL |
| Process | TSMC 40nm LP |
| VCO Operating Range (MHz) | 640 - 1056 |
| Input Freq (MHz) | 10 - 132 |
| Output Freq Range (MHz) | 80 - 1056 |
| Analog Supply Voltage (V) | 1.04 - 1.26 |
| Digital Supply Voltage (V) | 1.045 - 1.26 |
| Spread Spectrum | Yes |
| Temp. Range (°C) | -40°C to +125°C |
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