Features
- FPD-Link Receiver can be used for an analog receiver with the ANSI/TIA/EIA-644 interface (Except for the voltage range of VIN)
- Technology: TSMC 28nm HPC+ (High-Performance Compact Plus) 1p10M
- Supply voltage can be applied at 1.0V for overdrive of the core voltage, 1.8V for the I/O voltage
- With an input clock at 71.5MHz, the maximum data rate of each channel is 500Mbps
- Clock Monitor function can detect an anomaly status of the input clock (CLK_P/N) and the Phase-Locked Loop (PLL) output clock
Flat Panel Display Link Receiver IP (TSMC 28nm HPC+) Block Diagram
Description
Renesas' Flat Panel Display Link (FPD-Link) Receiver is a useful 5-channel LVDS receiver. This IP enables the 1:7 serial-to-parallel conversion of TSMC's 28nm HPC+ (High-Performance Compact Plus) process.
Parameters
| Attributes | Value |
|---|---|
| Protocol | FPD-Link |
| Function | Receiver |
| Process | TSMC 28nm HPC+ |
| Data Rate (Mbps) | 500 |
| Interface | LVDS |
| Number of Channels | 5 |
| Input Freq (MHz) | 71.5 - 71.5 |
| Supply Voltage Range (V) | Core: 1.0V, I/O: 1.8V |
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