Features
- Can be used for an analog transceiver for the Universal Serial Bus Specification Revision 2.0 Full/Low-Speed interface
- Technology is TSMC's 22nm ULL (Ultra-Low Leakage) 1p9M
- Supply voltage can be applied - 1.1V for core voltage and 3.3V for I/O voltage
- USB transfer mode is Full-Speed (12Mbps) and Low-Speed (1.5Mbps) modes
- A terminal resistance, pull-up resistor, and pull-down resistor are included
USB 2.0 Full-Speed Transceiver IP Block Diagram
Description
Renesas' USB 2.0 Full-Speed (FS) Transceiver is a useful analog single-port transceiver hard macro. Fabricated using TSMC's 22nm ULL (Ultra-Low Leakage) process, this macro can be configured to operate as a USB 2.0 Full/Low-Speed peripheral or host controller.
For this IP, only the parts required for Full-Speed (12Mbps) and Low-Speed (1.5Mbps) are cut out from the USB 2.0 PHY IP. When High-Speed (480Mbps) is not required, the optimum solution in terms of area and power consumption can be provided.
Parameters
| Attributes | Value |
|---|---|
| Protocol | USB 2.0 FS |
| Function | PHY, Transceiver |
| Process | TSMC 22nm ULL |
| Data Rate (Mbps) | 12, 1.5 |
| Interface | - |
| Number of Channels | 1 |
| Supply Voltage Range (V) | Core: 1.1V, I/O: 3.3V |
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