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Renesas Electronics Corporation

Renesas’ Timing product portfolio has been acquired by SiTime.

Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.

Alternative(s) Available

Features

  • 8 – 0.7V low-power HCSL-compatible output pairs
  • LP-HCSL outputs with Zo = 85ohms ; save power and board space - no termination resistors required.
  • Space-saving 48-pin VFQFPN package
  • Fixed feedback path for 0ps input-to-output delay
  • 8 OE# pins; hardware control of each output
  • PLL or bypass mode; PLL can dejitter incoming clock
  • 100MHz or 133MHz PLL mode operation; supports PCIe and QPI applications
  • Selectable PLL bandwidth; minimizes jitter peaking in downstream PLL's
  • Spread Spectrum Compatible; tracks spreading input clock for low EMI
  • Cycle-to-cycle jitter < 50ps
  • Output-to-output skew < 65 ps
  • Input-to-output delay variation < 50ps
  • PCIe Gen3 phase jitter < 1.0ps RMS
  • QPI/UPI 9.6GT/s 12UI phase jitter < 0.2ps RMS

Description

The 9ZXL0851 is a low-power 8-output differential buffer that meets all the performance requirements of the Intel DB1200ZL specification. It is suitable for PCI-Express Gen1/2/3 or QPI/UPI applications, and uses a fixed external feedback to maintain low drift for demanding QPI/UPI applications.

Parameters

AttributesValue
Diff. Outputs8
Diff. Output SignalingLP-HCSL
Output Freq Range (MHz)25 - 150
Diff. Inputs1
Diff. Input SignalingHCSL
Accepts Spread Spec InputYes
Power Consumption Typ (mW)445
Supply Voltage (V)3.3 - 3.3
Output TypeLP-HCSL
Diff. Termination Resistors16
Package Area (mm²)36
Battery BackupNo
Battery SealNo
CPU Supervisory Function PORNo
Crystal Frequency TrimmingNo
Frequency Out PinNo
Inputs (#)1
Input Freq (MHz)33 - 150
FunctionBuffer
Input TypeHCSL
Output Voltage (V)0.7
Product CategoryProcessor Clock Buffers

Package Options

Pkg. TypePkg. Dimensions (mm)Lead Count (#)Pitch (mm)
VFQFPN6.0 x 6.0 x 0.9480.4

Application Block Diagrams

Genoa Server Block Diagram
AMD 4th-Gen EPYC (Genoa) Power & Timing System
Complete power and timing system for AMD Genoa with SVI3, DDR5, and PCIe Gen 5/6 support.

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