Renesas’ Timing product portfolio has been acquired by SiTime.

Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.

9P936

Low Skew Dual Bank DDR I/II Fan-out Buffer

Features

Low skew, fanout buffer
SMBus for functional and output control
Single bank 1-6 differential clock distribution
1 pair of differential feedback pins for input to output synchronization
Supports up to 2 DDR DIMMs
266MHz (DDRI 533) output frequency support
400MHz (DDRII 800) output frequency support
Programmable skew through SMBus
Individual output control programmable through SMBus
OUTPUT - OUTPUT skew: <100ps
Output Rise and Fall Time for DDR outputs: 650ps - 950ps
DUTY CYCLE: 47% - 53%
28-pin SSOP/TSSOP package
RoHS compliant packaging

Find Other Products in Clock Distribution

9P936 - Block Diagram

9P936 - Pinout

9P936 - Block Diagram

9P936 - Pinout

Description

Dual DDR I/II fanout buffer for VIA Chipset

Applied Filters:

Loading Loading