Features
- 6 - 100 MHz Differential low power push pull (HCSL compatible) output pairs
- 32-pin QFN; space-savings
- Push Pull outputs
- Low power consumption, reduced component count
- PCIe Gen2
- Spread spectrum capability; reduced EMI when needed
- D2/D3 SMBus Write/Read SMBus address
- Cycle-to-cycle jitter <125 ps
- Output-to-output skew < 100 ps
- Current consumption < 40 mA
- PCIe Gen2 phase jitter < 3.0 ps RMS
9FGL699 - Block Diagram
Description
The 9FGL699 is a 6-output low-power clock sythesizer for PCIe Gen2. It runs from a 25 MHz XTAL, provides spread spectrum capability, and has an SMBus for software control of the device.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9FGL699AKLF | Obsolete | N/A | Out of Stock | VFQFPN | 32# | Tray | 3 | 0 | 490# | Yes | e3 Sn | 0 to 70°C |
| 9FGL699AKLFT | Obsolete | N/A | Out of Stock | VFQFPN | 32# | Reel | 3 | 2500# | 0 | Yes | e3 Sn | 0 to 70°C |
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- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
- End Of Life NoticePDF 1.22 MB Sep 07, 2022
- End Of Life NoticePDF 1.15 MB Aug 15, 2022
- Product Change NoticePDF 728 KB May 13, 2022
- Application NotePDF 307 KB 7WDXRDKU4E7E-5-59989 Mar 10, 2016
- Application NotePDF 235 KB 7WDXRDKU4E7E-5-58851 Apr 08, 2015
- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
- Application NotePDF 1.9 MB 7WDXRDKU4E7E-5-57315 May 13, 2014
- Application NotePDF 495 KB 7WDXRDKU4E7E-5-57312 May 12, 2014
- Application NotePDF 442 KB 7WDXRDKU4E7E-5-57298 May 08, 2014
- Application NotePDF 115 KB 7WDXRDKU4E7E-5-57294 May 07, 2014
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- Application NotePDF 431 KB 7WDXRDKU4E7E-5-59216 Dec 06, 2023
- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
- Application NotePDF 307 KB 7WDXRDKU4E7E-5-59989 Mar 10, 2016View More (17)
Application Notes & White Papers (17)
- End Of Life NoticePDF 1.22 MB Sep 07, 2022
- End Of Life NoticePDF 1.15 MB Aug 15, 2022
- Product Change NoticePDF 728 KB May 13, 2022
- Product Change NoticePDF 983 KB Jun 25, 2019
- Product Change NoticePDF 583 KB 7WDXRDKU4E7E-5-61343 Dec 20, 2016View More (8)
Product Notices (PCN, EOL, etc) (8)
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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