Skip to main content
Renesas Electronics Corporation - June is Pride Month, a month to raise awareness of the rights and the culture of the LGBTQ+ community

Features

  • Four independent timing channels
  • Jitter output below 150fs RMS (typical)
  • Digital PLLs (DPLLs) lock to any frequency from 0.5Hz to 1GHz
  • DPLLs/Digitally Controlled Oscillators (DCOs) generate any frequency from 0.5Hz to 1GHz
  • DCO outputs can be aligned in phase and frequency with the outputs of any DPLL or DCO
  • DPLLs comply with ITU-T G.8262 for Synchronous Ethernet (SyncE)
  • IEEE 1588 Support:
    • DCOs can be controlled by external IEEE 1588 software to synthesize Precision Time Protocol (PTP)/IEEE 1588 clocks with frequency resolution less than 1.11x10-16
    • Combo Bus simplifies compliance with ITU-T G.8273.2
    • Precise (1ps) resolution for phase measurement and control
    • All outputs/inputs can be configured to decode/encode PWM clock signals
    • PWM can be used to transmit and receive embedded frame and sync pulses; as well as Time of Day (ToD) and other data
  • Device requires a crystal oscillator or fundamental-mode crystal: 25MHz to 54MHz
  • Optional XO_DPLL input allows a wider range for XO, TCXO, or OCXO frequencies from 1MHz to 150MHz for applications that require a local oscillator with high stability
  • Serial processor ports support 1MHz I²C or 50MHz SPI

Description

The 8A34002 system synchronizer for IEEE 1588 generates ultra-low jitter precision timing signals based on the IEEE 1588 Precision Time Protocol (PTP) and Synchronous Ethernet (SyncE). The device can be used as a single timing and synchronization source for a system or two of them can be used as a redundant pair for improved system reliability. Digitally Controlled Oscillators (DCOs) are available to be controlled by IEEE 1588 clock recovery servo software running on an external processor. The device supports physical layer timing with Digital PLLs (DPLLs) and other timing blocks necessary to implement a Synchronous Equipment Timing Source (SETS) for SyncE. The DCOs can be controlled using IEEE 1588 information alone, or they can combine IEEE 1588 time information with physical layer frequency information from SyncE in accordance with ITU-T G.8273.2. The device can be used to actively measure and compensate for clock propagation delays across backplanes and across circuit boards to ensure the distribution of accurate time and phase with minimal time error between IEEE 1588 Time Stamp Units (TSUs) in a system. The device supports multiple independent channels that control IEEE 1588 clock synthesis, SyncE clock generation, jitter attenuation, and universal frequency translation. Input-to-input, input-to-output and output-to-output phase skew can all be precisely managed. The device outputs ultra-low jitter clocks that can directly synchronize SerDes running at up to 28Gbps, as well as CPRI/OBSAI, SONET/SDH and PDH interfaces and IEEE 1588 TSUs.

To easily implement synchronization in IEEE 1588 systems, Renesas offers PTP Clock Manager Software for free under license.

Parameters

AttributesValue
Diff. Outputs8
Output Freq Range (MHz)5.0E-7 - 1000
Diff. Inputs7
Output TypeHSTL, LVCMOS, LVDS, LVHSTL, LVPECL, LVTTL
Battery BackupNo
Battery SealNo
CPU Supervisory Function PORNo
Crystal Frequency TrimmingNo
Frequency Out PinNo
Inputs (#)14
Input Freq (MHz)5.0E-7 - 1000
Channels (#)4
FunctionSystem Synchronizer
Input TypeHCSL, LVDS, LVHSTL, LVPECL, SSTL
Output Banks (#)4
Core Voltage (V)2.5V, 3.3V
Output Voltage (V)1.2V, 1.5V, 1.8V, 2.5V, 3.3V
Product CategoryIEEE 1588, ClockMatrix, Ultra-Low Jitter Clocks (<300 fs RMS), Jitter Attenuators, Network Synchronization, Programmable Clocks

Package Options

Pkg. TypePkg. Dimensions (mm)Lead Count (#)Pitch (mm)
VFQFPN10.0 x 10.0 x 1.0720.5

Complete Your Design

Explore complementary products to elevate your design

Part NumberStatusSamplesLongevityStockPackageBudgetary Price (USD)Lead Count (#)Carrier TypeMoisture Sensitivity Level (MSL)Qty. per Reel (#)Qty. per Carrier (#)Pb (Lead) FreePb Free CategoryTemp. Range (°C)Country of AssemblyCountry of Wafer Fabrication
8A34002E-000NLGActiveAvailable2040 AprIn StockVFQFPN1ku | $23.7372#Tray30168#Yese3 Sn-40 to 85°CCHINASINGAPORE
8A34002E-000NLG#ActiveN/A2040 AprOut of StockVFQFPN1ku | $23.7372#Reel32500#0Yese3 Sn-40 to 85°CCHINASINGAPORE
8A34002E-000NLG8ActiveN/A2040 AprIn StockVFQFPN1ku | $23.7372#Reel32500#0Yese3 Sn-40 to 85°CCHINASINGAPORE
8A34002B-000NLGObsoleteN/AOut of StockVFQFPN72#Tray30168#Yese3 Sn-40 to 85°C
8A34002B-000NLG#ObsoleteN/AOut of StockVFQFPN72#Reel32500#0Yese3 Sn-40 to 85°C
8A34002B-000NLG8ObsoleteN/AOut of StockVFQFPN72#Reel32500#0Yese3 Sn-40 to 85°C
8A34002C-000NLGObsoleteN/AOut of StockVFQFPN72#Tray30168#Yese3 Sn-40 to 85°C
8A34002C-000NLG#ObsoleteN/AOut of StockVFQFPN72#Reel32500#0Yese3 Sn-40 to 85°C
8A34002C-000NLG8ObsoleteN/AOut of StockVFQFPN72#Reel32500#0Yese3 Sn-40 to 85°C
8A34002PB-000NLGObsoleteN/AOut of StockVFQFPN72#Tray30168#Yese3 Sn-40 to 85°C
8A34002PB-000NLG#ObsoleteN/AOut of StockVFQFPN72#Reel32500#0Yese3 Sn-40 to 85°C
8A34002PB-000NLG8ObsoleteN/AOut of StockVFQFPN72#Reel32500#0Yese3 Sn-40 to 85°C
8A34002PC-000NLGObsoleteN/AOut of StockVFQFPN72#Tray30168#Yese3 Sn-40 to 85°C
8A34002PC-000NLG#ObsoleteN/AOut of StockVFQFPN72#Reel32500#0Yese3 Sn-40 to 85°C
8A34002PC-000NLG8ObsoleteN/AOut of StockVFQFPN72#Reel32500#0Yese3 Sn-40 to 85°C

Complete Your Design

Explore complementary products to elevate your design

Support Communities

  1. 8A34002, I2C interface

    Good afternoon. I have one problem with 8A34002 and I2C slave interface. When I try to read register value (JTAG_DEVICE_ID or PRODUCT_ID), I have to read 2 bytes twice. (1 attempt reading - I get 2 bytes but only 1 correct, on second attempt reading - I get a ...

    Jul 26, 2023
  2. 8A34002xtal使用TCXO来替代xo的晶振是否可行

    SYNCE的产品,如果只在xtal上使用txco,而不是xo是tcxo,xtal是晶体得方案,从而节省一个晶体是否可行,以及GPIO引脚能否作为PTP_event从 ...

    Dec 23, 2025
  3. 8A34004 and White Rabbit

    I am planning to implement CERN White Rabbit protocol using 8A34004 ClockMatrix solution. It seems possible to me - using this chip as high precision phase measurement on master side (1ps resolution) and as high precision phase write DCO on the slave side (again, with 1ps resolution). Did someone use such ...

    Nov 27, 2024
Support Communities

Support Communities

Get quick technical support online from Renesas Engineering Community technical staff.
Browse Articles

Knowledge Base

Browse our knowledge base for helpful articles, FAQs, and other useful resources.
Submit a Ticket

Submit a Ticket

Need to ask a technical question or share confidential information?