Features
- 48 PCIe Gen1 Lanes, 12 Switch Ports
- Non-blocking switch architecture optimized for High Performance System Interconnect
- Partionable switch architecture for true multi-root support
- Internal buffering and flow control credits optimized for maximum bandwidth and large payloads
- Low latency, Low power
89HPES48H12 - Block Diagram
Description
Provides 48 PCIe lanes and 12 ports of high-performance, deterministic system interconnect switching. All ports receive full line rate, non-blocking throughput for multiple traffic flows regardless of switch loading.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Temp. Grade | Pb (Lead) Free | Carrier Type |
|---|---|---|---|---|---|---|---|---|
| 89HPES48H12ZABL | Obsolete | N/A | Out of Stock | FCBGA | 1156# | C | No | Tray |
| 89HPES48H12ZABLI | Obsolete | N/A | Out of Stock | FCBGA | 1156# | I | No | Tray |
| 89HPES48H12ZABR | Obsolete | N/A | Out of Stock | FCBGA | 1156# | C | No | Tray |
| 89HPES48H12ZABRI | Obsolete | N/A | Out of Stock | FCBGA | 1156# | I | No | Tray |
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- Manual - Development ToolsPDF 2.56 MB 7WDXRDKU4E7E-5-49851 Dec 03, 2010
- Application NotePDF 167 KB 7WDXRDKU4E7E-5-49327 Nov 16, 2007
- Application NotePDF 250 KB 7WDXRDKU4E7E-5-49335 May 24, 2007
- Manual - HardwarePDF 6.79 MB 7WDXRDKU4E7E-5-49251 Jan 01, 2007
- Product Change NoticePDF 115 KB 7WDXRDKU4E7E-5-55232 Apr 10, 2013
- Product Change NoticePDF 114 KB 7WDXRDKU4E7E-5-55153 Mar 26, 2013
- Device Errata
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- Manual - Development ToolsPDF 2.56 MB 7WDXRDKU4E7E-5-49851 Dec 03, 2010
- Manual - HardwarePDF 6.79 MB 7WDXRDKU4E7E-5-49251 Jan 01, 2007
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- Application NotePDF 167 KB 7WDXRDKU4E7E-5-49327 Nov 16, 2007
- Application NotePDF 250 KB 7WDXRDKU4E7E-5-49335 May 24, 2007
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- End Of Life NoticePDF 647 KB 7WDXRDKU4E7E-5-61717 Jul 03, 2017
- End Of Life NoticePDF 898 KB 7WDXRDKU4E7E-5-61679 Jun 01, 2017
- Product Change NoticePDF 524 KB 7WDXRDKU4E7E-5-59640 Oct 29, 2015View More (8)
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- Device Errata
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