The 8SLVS1118 is a high-performance, low-power, differential 1:18 output fanout buffer. This highly versatile device is designed for the fanout of high-frequency, very low additive phase-noise clock and data signals. Guaranteed output-to-output and part-to-part skew characteristics make the 8SLVS1118 ideal for clock distribution applications that demand well-defined performance and repeatability. The device is characterized to operate from a 2.5V or 3.3V power supply. The integrated bias voltage references enable easy interfacing AC-coupled signals to the device inputs.

特長

  • 1:18, low skew, low additive jitter LVPECL/LVDS fanout buffer 
  • Low power consumption 
  • Differential PCLK, nPCLK clock pair accepts the following differential/single-ended input levels: LVDS, LVPECL, and LVCMOS 
  • Maximum input clock frequency: 2GHz 
  • Propagation delay: 290ps (typical) 
  • Output skew: 40ps (typical) 
  • Low additive phase jitter, RMS: 39fs (typical)
  • Integration range: 12kHz–20MHz (fREF = 156.25MHz, VPP = 1V, VDD = 3.3V) 
  • Full 2.5V and 3.3V supply voltage modes 
  • Device current consumption:
    • 180mA (typical) IEE for LVPECL output mode
    • 400mA (typical) IDD for LVDS output mode 
  • 48-VFQFN, lead-free (RoHS 6) packaging 
  • Transistor count: 1762
  • -40°C to +85°C ambient operating temperature 
  • Supports case temperature up to 105°C

製品選択

発注型名 Part Status Type Lead Count (#) Temp. Grade Pb (Lead) Free Carrier Type 購入/サンプル
Active 48 I はい Tray
Availability
Active 48 I はい Reel
Availability
Active 48 I はい Reel
Availability

ドキュメント&ダウンロード

タイトル 他の言語 分類 形式 サイズ 日付
データシート
8SLVS1118 Datasheet データシート PDF 666 KB
アプリケーションノート、ホワイトペーパー
AN-828 Termination - LVPECL アプリケーションノート PDF 322 KB
AN-844 Termination - AC Coupling Clock Receivers アプリケーションノート PDF 170 KB
AN-842 Thermal Considerations in Package Design and Selection アプリケーションノート PDF 495 KB
AN-840 Jitter Specifications for Timing Signals アプリケーションノート PDF 442 KB
AN-833 Differential Input Self Oscillation Prevention アプリケーションノート PDF 180 KB
AN-834 Hot-Swap Recommendations アプリケーションノート PDF 153 KB
AN-836 Differential Input to Accept Single-ended Levels アプリケーションノート PDF 120 KB
AN-827 Application Relevance of Clock Jitter アプリケーションノート PDF 1.15 MB
AN-815 Understanding Jitter Units アプリケーションノート PDF 565 KB
AN-805 Recommended Ferrite Beads アプリケーションノート PDF 121 KB
PCN / PDN
PCN# : A1904-01 Add Greatek, Taiwan as an Alternate Assembly Facility 製品変更通知 PDF 983 KB
Downloads
8SLVS1118 IBIS Model モデル-IBIS ZIP 55 KB
その他資料
IDT Clock Distribution Overview (Japanese) English 概要 PDF 7.79 MB
RF Timing Family Product Overview 概要 PDF 464 KB
Timing Solutions Products Overview 概要 PDF 4.11 MB
IDT Products for Radio Applications (Japanese) English 製品概要 PDF 6.27 MB
IDT Clock Generation Overview (Japanese) English 概要 PDF 2.19 MB