RH850 Multicore Model-Based Environment [Embedded Target for RH850 Multicore]

Overview

The Embedded Target for RH850 Multicore is a RH850 model-based multicore environment that simplifies complex driving control for the autonomous-driving era. In addition to the multicore support of the PILS (Note) tool for automatic configuration of environments, Embedded Target for Renesas CS+, it can also be interlinked with a model-based parallelization tool from eSOL Co., Ltd.

The Embedded Target for RH850 Multicore generates parallel code for multicore RH850 devices through the implementation phase of a Simulink® model from The MathWorks®, Inc. It contributes to innovative automotive control systems for “eco-cars” (fuel economy and CO2 regulation) and to enhanced safety through the evaluation of functionality and performance in the flow of development.

We are also developing another product for systems with multiple control periods (multi-rate control), as systems such as those for engine and body control generally require.

Note

PILS: Processor In the Loop Simulation

Release Information

  • The Embedded Target for RH850, which supports the block unit performance analysis of the single core is also available.
  • To purchase the tool, contact your local Renesas Electronics marketing office or distributor for release date.

Operating Environment

Type of License

Annual license, i.e. a license with a one-year expiry period. Contact your nearest Renesas distributor with regard to purchasing products.

Functions

  • Generation of code for verifying algorithms from Simulink models
  • Automatic generation of Processor in the Loop Simulation (PILS) environments

Features

Graphical display of the states of execution for each core in sub-system units of Simulink models
Acquisition of execution times in sub-system units at the time of simulation through the debugger of CS+
Graphical display of the states of execution for each core in sub-system units
⇒ The allowable margins for processing, for which the worst execution timespans during simulation are going to be the control periods, can be checked
Automatically finds the best allocations of cores for complex innovative control systems then parallelizes them
Automatically finds the best core allocations for control systems in cooperation with the MBP tool from eSOL Co., Ltd.
⇒ This makes it possible to compare and examine which software structures make effective use of the capacity of the multiple cores directly on MATLAB and Simulink models
Automatically generates parallel source code and provides visualization of the performance of multiple cores during modelling
⇒ Returning to earlier stages in design due to incorrect estimation of parallel performance before implementing software can be avoided, and the development times for multicore control software can be shortened
Cycle-accurate simulators as optional features of CS+, which allow the measurement of times that closely reflect those of actual systems. (For some of the RH850 MCUs)
Cycle-Accurate Simulator for RH850 >>

Flow of Operations

  1. 1. Measuring execution times: The execution times of a Simulink model are measured in sub system units by using the software trace function of the debugger of CS+ on PILS of a single core. (This function is also supported even Embedded Target for RH850.)
  2. 2. Finding the optimal core allocation: A search for the best core allocation based on the execution times acquired in step 1 is conducted through interlinked operation with the optional “eSOL MBP Renesas RH850 MBD Package” (provisional name) of the Model-Based Parallelizer (provisionally referred to as eSOL MBP in this document) from eSOL, and parallelization proceeds.
  3. 3. Code generation: Synchronous processing is automatically allocated among the cores in accord with the core allocation plan from the model-based parallelization tool or an allocation plan specified by the user, and parallel source code for the RH850 is generated by the Embedded Coder from The MathWorks, Inc.
  4. 4. Re-measuring execution time: The execution times with the cores having been allocated in sub-system units are acquired by the debugger function of CS+, and the states of execution for each core are displayed in a graph.

Target Devices

The Embedded Target for RH850 Multicore supports the MCUs listed below.

Contact our distributors regarding our plans in regard to support for the other MCUs, i.e. those for which we do not currently provide a cycle-accurate simulator.

Series Applicable MCU Cycle-accurate simulator
RH850/C1x RH850/C1H Yes
RH850/E1x RH850/E1M-S2 (Note1) Please contact us.
RH850/F1x RH850/F1L, RH850/F1K, RH850/F1KM, RH850/F1H Under planning
RH850/P1x-C RH850/P1H-C, RH850/P1M-C Yes

Note

  1. 1. Use only main CPU.

Video

The video introduces the Embedded Target for RH850 Multicore. (Renesas DevCon Japan 2017)

Related Information

The Embedded Target for RH850 Multicore is a product from Renesas that has become practically applicable through the results of research and development by Renesas in collaboration with the Parallel and Distributed Systems Lab at Nagoya University, with the assistance of Program for Strategic Innovative Energy Saving Technology of the New Energy and Industrial Technology Development Organization.

Company names and product names are the registered names and trademarks of the given companies.

Information supporting development tools

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