The R1Q2A4436RBG is a 4, 194, 304-word by 36-bit and the R1Q2A4418RBG is a 8, 388, 608-word by 18-bit synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are suitable for applications which require synchronous operation, High-Speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin plastic FBGA package.

Features

  • Power Supply 1.8 V for core (VDD), 1.4 V to VDD for I/O (VDDQ)
  • Clock Fast clock cycle time for high bandwidth Two input clocks (K and /K) for precise DDR timing at clock rising edges only Two input clocks for output data (C and /C) to minimize clock skew and flight time mismatches Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems Clock-stop capability with μs restart
  • I/O Separate independent read and write data ports with concurrent transactions 100% bus utilization DDR read and write operation HSTL I/O User programmable output impedance PLL circuitry for wide output data valid window and future frequency scaling
  • Function Two-tick burst for low DDR transaction size Internally self-timed write control Simple control logic for easy depth expansion JTAG 1149.1 compatible test access port
  • Package 165 FBGA package (15 x 17 x 1.4 mm)

Product Options

Orderable Part ID Part Status Pkg. Type Carrier Type Buy Sample
R1Q2A4418RBG-40IB0
Active LBGA Tray
Availability

Documentation & Downloads

Title Other Languages Type Format File Size Date
Datasheets & Errata
R1Q2A4436RBG, R1Q2A4418RBG Datasheet PDF 930 KB
PCNs & PDNs
Unification of a JEDEC tray and a embossed carrier tape for LQFP package (Additional Information & Correction) 日本語 Product Change Notice PDF 4.86 MB
Unification of a JEDEC tray and a embossed carrier tape for LQFP package 日本語 Product Change Notice PDF 3.74 MB
Unification of a JEDEC tray and a embossed carrier tape for LQFP package 日本語 Product Change Notice PDF 1.46 MB
Downloads
R1Q2A4418RBG-40I Verilog model for VCS 日本語 Model - IBIS VP 83 KB
R1Q2A4418RBG-40I Verilog model for Verilog XL 日本語 Model - IBIS VP 80 KB
R1Q2A4418RBG-40I Verilog model for Model Sim 日本語 Model - IBIS VP 26 KB
R1Q2A4418RBG-40I Verilog model for NC Verilog 日本語 Model - IBIS VP 96 KB
R1Q2A4418RBG-40I IBIS 日本語 Model - IBIS IBS 1.79 MB
R1Q2A4418RBG-40I BSDL 日本語 Model - IBIS BSDL 9 KB
Other
Network Packet Search Solution Catalog Brochure PDF 1.79 MB