The 9DBV0441 is a member of Renesas' SOC-Friendly 1.8V Very-Low-Power (VLP) PCIe family. It has integrated output terminations providing Zo = 100Ω for direct connection to 100Ω transmission lines. The device has 4 output enables for clock management, and 3 selectable SMBus addresses.
Features
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Direct connection to 100Ω transmission lines; saves 16 resistors compared to standard HCSL outputs
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53mW typical power consumption in PLL mode; minimal power consumption
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Spread Spectrum (SS) compatible; allows use of SS for EMI reduction
- OE# pins: support DIF power management
- HCSL compatible differential input: can be driven by common clock sources
- Programmable slew rate for each output: allows tuning for various line lengths
- Programmable output amplitude: allows tuning for various application environments
- Pin/software selectable PLL bandwidth and PLL Bypass: minimize phase jitter for each application
- Outputs blocked until PLL is locked: clean system start-up
- Software selectable 50MHz or 125MHz PLL operation: useful for Ethernet applications
- Configuration can be accomplished with strapping pins: SMBus interface not required for device control
- 3.3V tolerant SMBus interface works with legacy controllers
- Space-saving 5 × 5 mm 32-VFQFPN: minimal board space
- Selectable SMBus addresses: multiple devices can easily share an SMBus segment