Overview
Description
3.3V Phase lock loop, 1:10 Clock driver, zero delay buffer. With the 74ALVCF162835A provides a complete solution for PC-100 and PC-133 SDRAM solutions.
Features
- Phase-Lock Loop Clock Distribution for Synchronous DRAM applications
- Distributes one clock input to one bank of ten outputs
- External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal
- Operates at 3.3V VDD
- tpd Phase Error at 166MHz: < ±150ps
- Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz
- Spread Spectrum Compatible
- Operating frequency 50MHz to 175MHz
Comparison
Applications
Design & Development
Models
ECAD Models
Schematic symbols, PCB footprints, and 3D CAD models from SamacSys can be found by clicking on the CAD Model links in the Product Options table. If a symbol or model isn't available, it can be requested directly from SamacSys.
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