特長
- 8 – 0.7V low-power HCSL-compatible output pairs
- LP-HCSL outputs with Zo = 85ohms ; save power and board space - no termination resistors required.
- Space-saving 48-pin VFQFPN package
- Fixed feedback path for 0ps input-to-output delay
- 8 OE# pins; hardware control of each output
- PLL or bypass mode; PLL can dejitter incoming clock
- 100MHz or 133MHz PLL mode operation; supports PCIe and QPI applications
- Selectable PLL bandwidth; minimizes jitter peaking in downstream PLL's
- Spread Spectrum Compatible; tracks spreading input clock for low EMI
- Cycle-to-cycle jitter < 50ps
- Output-to-output skew < 65 ps
- Input-to-output delay variation < 50ps
- PCIe Gen3 phase jitter < 1.0ps RMS
- QPI/UPI 9.6GT/s 12UI phase jitter < 0.2ps RMS
説明
The 9ZXL0851 is a low-power 8-output differential buffer that meets all the performance requirements of the Intel DB1200ZL specification. It is suitable for PCI-Express Gen1/2/3 or QPI/UPI applications, and uses a fixed external feedback to maintain low drift for demanding QPI/UPI applications.
パラメータ
| 属性 | 値 |
|---|---|
| Chipset Manufacturer | Intel |
| Clock Spec. | DB1200ZL |
| Diff. Outputs | 8 |
| Diff. Output Signaling | LP-HCSL |
| Output Enable (OE) Pins | 8 |
| Output Freq Range (MHz) | 25 - 150 |
| Diff. Inputs | 1 |
| Diff. Input Signaling | HCSL |
| Accepts Spread Spec Input | Yes |
| Power Consumption Typ (mW) | 445 |
| Advanced Features | HW PLL mode control |
| App Jitter Compliance | PCIe Gen1, PCIe Gen2, PCIe Gen3, QPI |
| Package Area (mm²) | 36 |
パッケージオプション
| Pkg. Type | Pkg. Dimensions (mm) | Lead Count (#) | Pitch (mm) |
|---|---|---|---|
| VFQFPN | 6.0 x 6.0 x 0.9 | 48 | 0.4 |
アプリケーション・ブロック図
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AMD第4世代EPYC (Genoa) パワー&タイミングシステム
SVI3、DDR5、PCIe Gen 5/6をサポートするAMD Genoa向けの完全な電源およびタイミングシステム。
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