特長
- Low skew, low jitter PLL clock driver
- Max frequency supported = 400MHz (DDRII 800)
- I2C for functional and output control
- Feedback pins for input to output synchronization
- Spread Spectrum tolerant inputs
- Programmable skew through SMBus
- Frequency defect control through SMBus
- Individual output control programmable through SMBus
説明
DDR I/DDR II Phase Lock Loop Zero Delay Buffer
適用されたフィルター