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Renesas’ Timing product portfolio has been acquired by SiTime.

Datasheets, documentation, and sample orders remain available on Renesas.com through late 2026. For new designs, purchasing, support, and product inquiries, visit SiTime.com or send an email to [email protected]. Full transition to SiTime is expected by late 2026.

9P935

Obsolete

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

Features

  • Low skew, low jitter PLL clock driver
  • Max frequency supported = 400MHz (DDRII 800)
  • I2C for functional and output control
  • Feedback pins for input to output synchronization
  • Spread Spectrum tolerant inputs
  • Programmable skew through SMBus
  • Frequency defect control through SMBus
  • Individual output control programmable through SMBus
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Description

DDR I/DDR II Phase Lock Loop Zero Delay Buffer

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