Overview

The 82P33714 Synchronous Equipment Timing Source (SETS) for Synchronous Ethernet (SyncE) provides tools to manage timing references, clock generation and timing paths for SyncE based clocks, per ITU-T G.8264 and ITU-T G.8262. 82P33714 meets the requirements of ITU-T G.8262 for synchronous Ethernet Equipment Clocks (EECs) and ITU-T G.813 for Synchronous Equipment Clocks (SEC). The device outputs low-jitter clocks that can directly synchronize Ethernet interfaces; as well as SONET/SDH and PDH interfaces. For 10G-40G SyncE single-board applications, see the 82P33731

IDT’s third generation Universal Frequency Translator family also includes the 8T49N285 (2-in / 1-PLL / 8-out), 8T49N286 (4-in / 2-PLL / 8-out), and 8T49N287 (2-in / 2-PLL / 8-out), and the 8T49N242 (2-in / 1-PLL / 4-out).

► Download the Altera and IDT Synchronous Ethernet Solution for ITU-T G.8262 white paper

  • Complies with ITU-T G.8262 for Synchronous Ethernet Equipment Clock (EEC), and G.813 for Synchronous Equipment Clock (SEC), and Telcordia GR-253-CORE for Stratum 3 and SONET Minimum Clock (SMC)
  • DPLLs lock to a wide range of reference clock frequencies including: 10/100/1000 Ethernet, 10G Ethernet, OTN, SONET/SDH, PDH, TDM, GSM, CPRI/OBSAI and GNSS frequencies using fractional-N input dividers
  • Generates clocks for: Ethernet, SONET/SDH and PDH interfaces: jitter generation <1 ps RMS (12 kHz to 20 MHz)
  • Automatic reference selection state machines select the active reference for each DPLL based on the reference monitors, priority tables, revertive and non-revertive settings and other programmable settings
  • Prevents output frequency corruption due to a bad PHY reference by accepting Loss of Signal (LOS) inputs from PHYs that immediately disqualify a reference
  • DPLL1 can be configured as a DCO (Digitally Controlled Oscillator) to support IEEE 1588 based clock generation under external processor control
  • Supports network timing master applications by locking to 1 PPS (Pulse Per Second) references from GPS or other GNSS sources
  • Eases local oscillator sourcing by supporting any of eight common TCXO/OCXO frequencies for the System Clock: 10 MHz, 12.8 MHz, 13 MHz, 19.44 MHz, 20 MHz, 24.576 MHz, 25 MHz or 30.72 MHz
  • Automatically loads configuration from an external EPROM after reset without processor intervention
  • 72 pin QFN package

Documentation

Title Type Date
PDF1.19 MB
Datasheet
PDF686 KB
Application Brief
PDF1.99 MB
Application Note
PDF148 KB
Application Note
PDF752 KB
Application Note
PDF324 KB
Application Note
PDF300 KB
Application Note
PDF249 KB
Application Note
PDF322 KB
Application Note
PDF606 KB
Application Note
PDF1.13 MB
Application Note
PDF1.11 MB
Application Note
PDF777 KB
Application Note
PDF170 KB
Application Note
PDF146 KB
Application Note
PDF133 KB
Application Note
PDF495 KB
Application Note
PDF442 KB
Application Note
PDF115 KB
Application Note
PDF233 KB
Application Note
PDF160 KB
Application Note
PDF120 KB
Application Note
PDF565 KB
Application Note
PDF202 KB
Application Note
PDF121 KB
Application Note
PDF438 KB
Application Note
PDF1.83 MB
Overview
PDF263 KB
Overview
PDF983 KB
Product Change Notice
PDF583 KB
Product Change Notice
PDF596 KB
Product Change Notice
PDF544 KB
Product Change Notice
PDF40 KB
Product Change Notice
PDF1.17 MB
White Paper

Design & Development

Software Downloads

Title Type Date
ZIP18.02 MB
Software & Tools - Other
TCP3.50 MB
Software & Tools - Other

Boards & Kits