Features
- Maximum ratings Supply voltage Vcc: 24 V Junction temperature Tj: –40 to +150°C
- Electrical characteristics VREF output voltage VREF: 5.0 V ± 1.5% UVLO operation start voltage Vuvlh: 10.5 V ± 0.7 V UVLO operation shutdown voltage Vuvll: 9.3 V ± 0.5 V UVLO hysteresis voltage Hysuvl: 1.2 V ± 0.5 V
- Functions Boost converter control with critical conduction mode Interleaving control with slave drop (SD) function at light load Off time control (OTC) function: Switching loss is decreased at light load. Brownout function Double OVP: Two line sense for over voltage protection Dynamic under voltage protection (DUVP): Sense for under voltage protection AC Hi voltage detection (ACDET) Feedback loop open detection ZCD signal open detection Master and Slave independenced over current protection 140 μs restart timer Package lineup: Pb-free SOP-20
Description
The R2A20132SP controls two boost converters to provide a active power factor correction. The R2A20132SP is based on R2A20112 and additional functions are Slave drop function at light load, Off time control, Brownout, Double OVP, Dynamic under voltage protection, and ZCD signal open detection. Also the reference voltage tolerance is improved. The R2A20132SP adopts critical conduction mode for power factor correction and realizes high efficiency and a low switching noise by zero current switching. Interleaving function improve ripple current on input or output capacitor by 180 degrees phase shift. The feedback loop open detection, over current protection are built in the R2A20132SP, and can constitute a power supply system of high reliability with few external parts.
| Part Number | Status | Samples | Stock | RoHS | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Pb (Lead) Free |
|---|---|---|---|---|---|---|---|---|---|
| R2A20132SP | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | SOP | 20# | Tape & Reel | No | |
| R2A20132SP#U0 | Obsolete | N/A | Out of Stock | RoHS:EN RoHS:JA | SOP | 20# | Tape & Reel | Yes | |
| R2A20132SP#W0 | Obsolete | Available | In Stock | Contact | SOP | 20# | Tape & Reel | 1 | Yes |
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- White PaperPDF 389 KB May 01, 2025The USB-C Power Delivery 3.1 Extended Power Range (EPR) standard enables charging up to 240W, supporting demanding applications such as high-performance laptops, power tools, and small appliances. This paper presents a complete wall-to-battery solution architecture based on USB-C PD 3.1 EPR, detailing the AC-DC adapter, USB-C PD charger, and battery management system. It demonstrates how the technology supports faster charging and greater device compatibility through a universal connector.
- Application NotePDF 799 KB R16AN0074EU0100 Rev.1.00 Mar 06, 2025AI-generated Summary: USB-C Power Delivery 3.1 Extended Power Range (EPR) enables up to 240W power delivery with voltages up to 48V and currents up to 5A, supporting fast and efficient charging for high-power devices such as laptops, portable power stations, and large displays. The system integrates a GaN-based high-efficiency AC/DC adapter, a bi-directional 48V charger, and a Battery Management System (BMS) with fuel-gauge firmware. Key design challenges include high-efficiency power conversion, voltage/current flexibility, bidirectional power flow, safety, and modular scalability. The solution provides reference designs, BOM, schematics, Gerber files, and firmware to accelerate product development and ensure compliance with regulatory standards.
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- Application NotePDF 1.3 MB R19AN0015ED0102 Rev.1.02 Jul 01, 2013AI-generated Summary: The document provides layout recommendations and design rules for a dual port Ethernet PHY device supporting 10Base-T, 100Base-TX, and 100Base-FX. It covers strap pin configuration options for initial start-up settings, detailing the use of pull-up and pull-down resistors, including recommended resistor values and schematic examples. The strap pins function only during power-up or reset, with internal and external resistor configurations advised for noise immunity. Additional chapters address media interfaces, power supply layout, clock input, LED control, and unused pins.
- Application NotePDF 1.21 MB R19AN0014ED0102 Rev.1.02 Jul 01, 2013AI-generated Summary: The document provides layout recommendations and design rules for Dual PHY and Single Channel PHY ASSP devices. It covers strap pin configuration options for initial start-up settings, including pull-up and pull-down resistor values and configurations to ensure stable operation in noisy environments. The layout guidelines include power supply design, differential pair routing, media-dependent interfaces, MAC interfaces, and clock input circuits. Examples and tables illustrate resistor values and schematic configurations for strap pins.
- Application NotePDF 224 KB R03AN0009EJ0100 Rev.1.00 Feb 22, 2012AI-generated Summary: The document explains the internal functions of the R2A20112A IC, focusing on its UVLO block which prevents operation under low voltage, and the 5 V reference voltage used internally. It details the Error Amplifier that stabilizes PFC output voltage, the Zero Current Detection circuit essential for CRM operation, and the RAMP generator that controls PWM ON time using external components. The drive stage outputs pulses to power MOSFETs with specific peak current capabilities and includes driver circuit examples for different MOSFET gate charges.
- Application NoteAI-generated Summary: The built-in oscillator frequency depends on an external resistor and a 10 pF capacitor, with a maximum 50% duty cycle at 48 kHz. The oscillator charges and discharges the capacitor between 0.2 V and 2 V. The error amplifier uses a transconductance amplifier to regulate output based on feedback voltage. The output pin drives an external MOSFET with up to 900 mA peak current. The peak current control circuit maintains constant inductor current using overcurrent protection via the CS pin. The constant ON time control uses feedback from the FB pin to regulate inductor current, adjusting peak current proportionally to input voltage for power factor correction.
- Application NotePDF 397 KB an1684 Jan 19, 2004AI-generated Summary: The document outlines important legal disclaimers and usage guidelines for semiconductor products. It emphasizes user responsibility for product design and safety, disclaims liability for damages, and clarifies no intellectual property licenses are granted. Products are categorized by quality grades with specific application recommendations. Users must comply with laws, avoid unauthorized modifications, and ensure safe use within specified conditions. Contact details for Renesas Electronics sales offices worldwide are provided.
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- White PaperPDF 389 KB May 01, 2025The USB-C Power Delivery 3.1 Extended Power Range (EPR) standard enables charging up to 240W, supporting demanding applications such as high-performance laptops, power tools, and small appliances. This paper presents a complete wall-to-battery solution architecture based on USB-C PD 3.1 EPR, detailing the AC-DC adapter, USB-C PD charger, and battery management system. It demonstrates how the technology supports faster charging and greater device compatibility through a universal connector.
- Application NotePDF 799 KB R16AN0074EU0100 Rev.1.00 Mar 06, 2025AI-generated Summary: USB-C Power Delivery 3.1 Extended Power Range (EPR) enables up to 240W power delivery with voltages up to 48V and currents up to 5A, supporting fast and efficient charging for high-power devices such as laptops, portable power stations, and large displays. The system integrates a GaN-based high-efficiency AC/DC adapter, a bi-directional 48V charger, and a Battery Management System (BMS) with fuel-gauge firmware. Key design challenges include high-efficiency power conversion, voltage/current flexibility, bidirectional power flow, safety, and modular scalability. The solution provides reference designs, BOM, schematics, Gerber files, and firmware to accelerate product development and ensure compliance with regulatory standards.
- Application NotePDF 1.3 MB R19AN0015ED0102 Rev.1.02 Jul 01, 2013AI-generated Summary: The document provides layout recommendations and design rules for a dual port Ethernet PHY device supporting 10Base-T, 100Base-TX, and 100Base-FX. It covers strap pin configuration options for initial start-up settings, detailing the use of pull-up and pull-down resistors, including recommended resistor values and schematic examples. The strap pins function only during power-up or reset, with internal and external resistor configurations advised for noise immunity. Additional chapters address media interfaces, power supply layout, clock input, LED control, and unused pins.
- Application NotePDF 1.21 MB R19AN0014ED0102 Rev.1.02 Jul 01, 2013AI-generated Summary: The document provides layout recommendations and design rules for Dual PHY and Single Channel PHY ASSP devices. It covers strap pin configuration options for initial start-up settings, including pull-up and pull-down resistor values and configurations to ensure stable operation in noisy environments. The layout guidelines include power supply design, differential pair routing, media-dependent interfaces, MAC interfaces, and clock input circuits. Examples and tables illustrate resistor values and schematic configurations for strap pins.
- Application NotePDF 224 KB R03AN0009EJ0100 Rev.1.00 Feb 22, 2012AI-generated Summary: The document explains the internal functions of the R2A20112A IC, focusing on its UVLO block which prevents operation under low voltage, and the 5 V reference voltage used internally. It details the Error Amplifier that stabilizes PFC output voltage, the Zero Current Detection circuit essential for CRM operation, and the RAMP generator that controls PWM ON time using external components. The drive stage outputs pulses to power MOSFETs with specific peak current capabilities and includes driver circuit examples for different MOSFET gate charges.View More (9)
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