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Features

  • Phase-Lock Loop Clock Distribution for Synchronous DRAM applications
  • Distributes one clock input to one bank of ten outputs
  • External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal
  • Operates at 3.3V VDD
  • tpd Phase Error at 166MHz: < ±150ps
  • Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz
  • Spread Spectrum Compatible
  • Operating frequency 50MHz to 175MHz

Description

3.3V Phase lock loop, 1:10 Clock driver, zero delay buffer.  With the 74ALVCF162835A provides a complete solution for PC-100 and PC-133 SDRAM solutions.  

Part NumberStatusSamplesStockPackageLead Count (#)Temp. GradePb (Lead) FreeCarrier Type
CSP2510DPGObsoleteN/AOut of StockTSSOP24#CNoTube
CSP2510DPG8ObsoleteN/AOut of StockTSSOP24#CNoReel
CSP2510DPGGObsoleteN/AOut of StockTSSOP24#CYesTube
CSP2510DPGG8ObsoleteN/AOut of StockTSSOP24#CYesReel
CSP2510DPGGIObsoleteN/AOut of StockTSSOP24#IYesTube
CSP2510DPGGI8ObsoleteN/AOut of StockTSSOP24#IYesReel
CSP2510DPGIObsoleteN/AOut of StockTSSOP24#INoTube
CSP2510DPGI8ObsoleteN/AOut of StockTSSOP24#INoReel
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