Features
- 15 - 0.7V current mode differential HSCL output pairs
- Pin compatible to 9EX21501/ Easy PCIe Gen3 upgrade
- 4 Selectable SMBus Addresses/Multiple devices can share the same SMBus Segment
- 8 dedicated and 2 group OE# pins/Hardware control of the outputs
- PLL or bypass mode/PLL can dejitter incoming clock
- Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's
- Spread Spectrum Compatible/tracks spreading input clock for low EMI
- SMBus Interface/unused outputs can be disabled
- Undriven differential outputs in Power Down mode/ Easy power management
- Cycle-to-cycle jitter <50ps
- Output-to-output skew < 150 ps
- PCIe Gen3 phase jitter < 1.0ps RMS
9EX21531 - Block Diagram
Description
The 9EX21531 provides 15 output clocks for PCIe Gen1/ 2/3 applications. The 9EX21531 has 4 selectable SMBus addresses, and dedicated CKPWRGD/PD# and VDDA pins for easy board design. A differential clock from a CK410B+ or CK420BQ main clock generator, such as the 932S421, drives the 9EX21531. In fanout mode, the 9EX21531 provides outputs up to 166MHz.
| Part Number | Status | Samples | Stock | Package | Lead Count (#) | Carrier Type | Moisture Sensitivity Level (MSL) | Qty. per Reel (#) | Qty. per Carrier (#) | Pb (Lead) Free | Pb Free Category | Temp. Range (°C) |
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 9EX21531AKLF | Obsolete | N/A | Out of Stock | VFQFPN | 64# | Tray | 3 | 0 | 207# | Yes | e3 Sn | 0 to 70°C |
| 9EX21531AKLFT | Obsolete | N/A | Out of Stock | VFQFPN | 64# | Reel | 3 | 3000# | 0 | Yes | e3 Sn | 0 to 70°C |
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- Application NotePDF 170 KB 7WDXRDKU4E7E-5-57318 May 13, 2014
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- Application NotePDF 1.99 MB 7WDXRDKU4E7E-5-57242 Mar 01, 2022
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- End Of Life NoticePDF 606 KB 7WDXRDKU4E7E-5-62524 Nov 29, 2017
- End Of Life NoticePDF 599 KB 7WDXRDKU4E7E-5-61808 Aug 24, 2017
- Product Change NoticePDF 583 KB 7WDXRDKU4E7E-5-61343 Dec 20, 2016
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This is the first video in our PCIe series. In this video, we define PCIe architectures, focusing on common and separate clock architectures. Watch the rest of the video series below where Ron will cover the impact of different timing architectures.
In this episode, Ron Wade from IDT (acquired by Renesas) explains PCIe common clocking and its impact on timing solutions. Learn about using a single clock source, fan-out buffers, and the considerations for spread spectrum and non-spread spectrum clocking in PCIe systems.
In this video, we explore PCIe with separate reference clocks and the effects of clock selection. Learn how separate reference clocks work and their impact on system performance and stability.
This video provides a high-level overview of Separate Reference Clock with Independent Spread (SRIS) architectures for PCI Express systems, additional performance requirements that this clocking architecture imposes on the reference clocks, and some system implications encountered trying to implement the architecture.
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